System-on-Chip Environment

SCE Version 2.2.0 Beta

Tutorial

Samar Abdi

Junyu Peng

Haobo Yu

Dongwan Shin

Andreas Gerstlauer

Rainer Doemer

Daniel Gajski

Copyright © 2003 CECS, UC Irvine

Table of Contents

1. Introduction

1.1. Motivation
1.2. SCE Goals
1.3. Models for System Design
1.4. System-on-Chip Environment
1.5. Design Example: GSM Vocoder
1.6. Organization of the Tutorial

2. System Specification Analysis

2.1. Overview

2.2. Specification Capture

2.2.1. SCE window
2.2.2. Open project
2.2.3. Open specification model
2.2.4. Browse specification model
2.2.5. View specification model source code

2.3. Simulation and Analysis

2.3.1. Simulate specification model
2.3.2. Profile specification model
2.3.3. Analyze profiling results

2.4. Summary

3. System Level Design

3.1. Overview

3.2. Architecture Exploration

3.2.1. Try pure software implementation
3.2.2. Estimate performance
3.2.3. Try software/hardware implementation
3.2.4. Estimate performance
3.2.5. Generate architecture model
3.2.6. Browse architecture model
3.2.7. Simulate architecture model (optional)

3.3. Software Scheduling and RTOS Model Insertion

3.3.1. Serialize behaviors
3.3.2. Generate serialized model
3.3.3. Simulate serialized model (optional)

3.4. Communication Synthesis

3.4.1. Select bus protocols
3.4.2. Map channels to buses
3.4.3. Generate communication model
3.4.4. Browse communication model
3.4.5. Simulate communication model (optional)

3.5. Summary

4. Custom Hardware Design

4.1. Overview

4.2. RTL Preprocessing

4.2.1. View behavioral input model
4.2.2. Generate SFSMD model
4.2.3. Browse SFSMD model
4.2.4. View SFSMD model (optional)
4.2.5. Simulate SFSMD model (optional)
4.2.6. Analyze SFSMD model

4.3. RTL Allocation

4.3.1. Allocate functional units
4.3.2. Allocate storage units
4.3.3. Allocate buses

4.4. RTL Scheduling and Binding

4.4.1. Schedule and bind manually (optional)
4.4.2. Schedule and bind automatically

4.5. RTL Refinement

4.5.1. Generate RTL model
4.5.2. Browse RTL model
4.5.3. View RTL model (optional)
4.5.4. View Verilog RTL model (optional)
4.5.5. Simulate RTL model (optional)

4.6. Summary

5. Embedded Software Design

5.1. Overview

5.2. SW code generation

5.2.1. Generate C code
5.2.2. Browse and View C code
5.2.3. Simulate C model (optional)

5.3. Instruction set simulation

5.3.1. Import instruction set simulator model
5.3.2. Simulate cycle accurate model

5.4. Summary

6. Conclusion

A. Frequently Asked Questions

List of Tables
6-1. Vocoder Refinement Effort

List of Figures
1-1. System-on-Chip Environment
1-2. GSM Vocoder
1-3. Task flow for system design with SCE
2-1. Specification analysis using SCE
3-1. System level design phase using SCE
4-1. Custom hardware generation using SCE
5-1. SW code generation with SCE

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