In this tutorial we presented the System on Chip design methodology. The SoC methodology defines the 4 models and 3 transformations that bring an initial system specification down to an RTL-implementation. In addition to validation through simulation, the well-defined nature of the models enables automatic model refinement, and application of formal methods, for example in verification.
The complete design flow was demostrated on an industrial strength example of the Vocoder Speech encoder.We have shown how SCE can take a specification model and allow the user to interactively provide synthesis decisions. In going from specification to RTL/Instruction-set model for the GSM Vocoder, we noted that compared to traditional manual refinement, the automatic refinement process gives us more than a 1000X productivity gain in modeling, since designers do not need to rewrite models.
Table 6-1. Vocoder Refinement Effort
| Refinement Step | Modified Lines | Manual Refinement | Automated Refinement |
|---|---|---|---|
| Spec -> Arch | 3,275 | 3~4 months | ~1 min. |
| Arch -> Comm | 914 | 1~2 months | ~0.5 min. |
| Comm -> RTL/IS | 6,146 | 5~6 months | ~2 min. |
Total. | 10,355. | 9~12 months. | ~4 mins. |
To draw the conclusion, SCE enables the designer to use the following powerful advantages that have never been available before.
Automatic model generation.
New models are generated by Automatic Refinement of abstract models. This means that the designer may start with a specification and simply use design decisions to automatically generate models reflecting those decisions.
Eliminates SLDL learning.
SCE eliminates the need for system-level design languages to be learnt by the designer. Only the knowledge of C for creating specification is required.
Enables non-experts to design.
This also enables non-experts to design systems. There is no need for the designer to worry about design details like protocol timing diagrams, low level interfaces etc. Consequently, software developers can design hardware and hardware designers can develop software.
Supports platforms.
SCE is great for platform based design . By limiting the choice of components and busses, designers may select their favorite architecture and then play around with different partitioning schema.
Customized methodology.
SCE can also be customized to any methodology as per the designer's choice of components, system architecture, models and levels of abstraction.
Enables IP trading.
SCE simplifies IP trading to a great extent by allowing interoperability at system level. With well defined wrappers, the designer can plug and play with suitable IPs in the design process. If an IP meets the design requirements, the designer may choose to plug that IP component in the design and not worry about synthesizing or validating that part of the design.