In this chapter, we covered the system level design phase of our methodology. With the rise in level of abstraction in system specification, it is no longer feasible to start designs at cycle accurate level. Instead, the specification should be gradually refined to derive a cycle accurate model. We saw three major steps in the system level design and synthesis process.
Architecture refinement took in the system specification model as input. Based on the profile of the specification, we chose the appropriate components to implement the desired system. We also delved into design space exploration by seeking a purely software solution. When the software solution turned out to be infeasible, we added a HW component to meet the real-time constraint of the design. We also demonstrated the power of automatic refinement to quickly come up with models and evaluate them, thereby greatly enhancing design space exploration. In the future, we will look at how to automate the decision making process, so that the tool can propose an optimal system architecture based on system constraints and available components.
Architecture refinement was followed by software scheduling and the RTOS insertion step. Although, for this demo, we did not need to insert any RTOS, it is a feature available in SCE. It allows for inclusion of useful task scheduling algorithms for dynamic scheduling. We also provide for static scheduling of tasks on both HW and SW.
The final major step of system level design is communication synthesis. We showed how the designer can use the database of a variety of bus models to construct a communication architecture for the design. Once the communication architecture is complete, the designers can assign abstract data transfers to a communication route in the architecture. Using automatic refinement in SCE, we showed how the designer could quickly produce a bus functional communication model and see if it fits the system requirements. This bus functional model serves as an input to the tasks of custom HW generation and SW code generation, which are described in the next two chapter. In the future, we would like to enhance the capabilities of our tool to perform automatic communication synthesis, whereby the tool can generate a good communication architecture and still meet system specification constraints.