The basic purpose of this tutorial is to guide a user through our System-on-Chip design environment (SCE). SCE helps designers to take an abstract functional description of the design and produce an implementation. We begin with a brief overview of our SoC methodology by describing the design flow and various abstraction levels. The overview also covers the user interfaces and the tools that support the design flow.
We then describe the example that we use throughout this tutorial. We selected the GSM Vocoder as an example for a variety of reasons. For one, the Vocoder is a fairly large design and is an apt representative of a typical component of a System-on-Chip design. Moreover, the functional specification of the Vocoder is well defined and publicly available from the European Telecommunication Standards Institute (ETSI).
The tutorial gives a step by step illustration of using the System-on-Chip Environment. Screenshots of the GUI are presented to aid the user in using the various features of SCE. (Please note that, depending on your specific version of the System-on-Chip Environment SCE and your system settings, the screen shots shown in this document may be slightly different from the actual display on your screen.) Over the course of this chapter, the user is guided on synthesizing the Vocoder model from an abstract specification to a clock cycle accurate implementation. The screenshots at each design step are supplemented with brief observations and the rationale for making design decisions. This would help the designer to gain an insight into the design process instead of merely following the steps. We wind up the tutorial with a conclusion and references. This tutorial assumes that the readers of this tutorial have basic knowledge of system design tasks and flow. In case the reader feels difficulty going following this tutorial, he can always go to the Appendix A: FAQ (Frequently Asked Questions) at the end of the tutorial to seek more explanation.
System-on-Chip capability introduces new challenges in the design process. For one, co-design becomes a crucial issue. Software and Hardware must be developed together. However, both Software and Hardware designers have different views of the system and they use different design and modeling techniques.
Secondly, the process of system design from specification to mask is long and elaborate. The process must therefore be split into several steps. At each design step, models must be written and relevant properties must be verified.
Thirdly, the system designers are not particularly fond of having to learn different languages. Moreover, writing different models and validating them for each step in the design process is a huge overkill. Designers prefer to create solutions rather than write several models to verify their designs.
It is with these aspects and challenges in mind that we have come up with a System-on-Chip Environment that takes off the drudgery of manual repetitive work from the designers by generating each successive model automatically according to the decisions made by the designers.