4.6. Summary

In this chapter we showed the task of custom HW design for the behaviors mapped to HW component. We started from a bus functional model of the system and isolated the behaviors that we want to implement in HW. These behaviors underwent a series of transformations to arrive at a FSMD style model that can serve as input to industry standard logic synthesis tools. Besides, generating the SpecC models, SCE is also capable of generating HW models in standard HDL like Verilog and Handel-C, which can be used by the Celoxica Design Kit.

We also saw various advantages of working with SCE during RTL synthesis. The environment and language allow the user to concentrate only on one behavior if he or she needs to. That is, the designer may choose to perform cycle a accurate implementation of a critical behavior and keep the remaining behaviors at a higher level of abstraction for fast simulation. The RTL synthesis process itself allows the designer to perform the scheduling and binding steps manually. However, we also showed the automatic RTL synthesis capabilities. The designer is free to tweak the synthesis results and generate a new model at any time.