Defines | |
#define | ENDM_P 0x00 |
#define | DMCTL_ENDM_P ENDM_P |
#define | ENDCPLB_P 0x01 |
#define | DMCTL_ENDCPLB_P ENDCPLB_P |
#define | DMC0_P 0x02 |
#define | DMCTL_DMC0_P DMC0_P |
#define | DMC1_P 0x03 |
#define | DMCTL_DMC1_P DMC1_P |
#define | DCBS_P 0x04 |
#define | PORT_PREF0_P 0x12 |
#define | PORT_PREF1_P 0x13 |
#define | ENDM 0x00000001 |
#define | ENDCPLB 0x00000002 |
#define | ASRAM_BSRAM 0x00000000 |
#define | ACACHE_BSRAM 0x00000008 |
#define | ACACHE_BCACHE 0x0000000C |
#define | DCBS 0x00000010 |
#define | PORT_PREF0 0x00001000 |
#define | PORT_PREF1 0x00002000 |
#define | ENIM_P 0x00 |
#define | IMCTL_ENIM_P 0x00 |
#define | ENICPLB_P 0x01 |
#define | IMCTL_ENICPLB_P 0x01 |
#define | IMC_P 0x02 |
#define | IMCTL_IMC_P 0x02 |
#define | ILOC0_P 0x03 |
#define | ILOC1_P 0x04 |
#define | ILOC2_P 0x05 |
#define | ILOC3_P 0x06 |
#define | LRUPRIORP 0x0D |
#define | ENIM 0x00000001 |
#define | ENICPLB 0x00000002 |
#define | IMC 0x00000004 |
#define | ILOC0 0x00000008 |
#define | ILOC1 0x00000010 |
#define | ILOC2 0x00000020 |
#define | ILOC3 0x00000040 |
#define | LRUPRIORST 0x00002000 |
#define | CPLB_VALID_P 0x00000000 |
#define | CPLB_LOCK_P 0x00000001 |
#define | CPLB_USER_RD_P 0x00000002 |
#define | CPLB_VALID 0x00000001 |
#define | CPLB_LOCK 0x00000002 |
#define | CPLB_USER_RD 0x00000004 |
#define | PAGE_SIZE_1KB 0x00000000 |
#define | PAGE_SIZE_4KB 0x00010000 |
#define | PAGE_SIZE_1MB 0x00020000 |
#define | PAGE_SIZE_4MB 0x00030000 |
#define | PAGE_SIZE_MASK 0x00030000 |
#define | PAGE_SIZE_SHIFT 16 |
#define | CPLB_L1SRAM 0x00000020 |
#define | CPLB_PORTPRIO 0x00000200 |
#define | CPLB_L1_CHBL 0x00001000 |
#define | CPLB_LRUPRIO 0x00000100 |
#define | CPLB_USER_WR 0x00000008 |
#define | CPLB_SUPV_WR 0x00000010 |
#define | CPLB_DIRTY 0x00000080 |
#define | CPLB_L1_AOW 0x00008000 |
#define | CPLB_WT 0x00004000 |
#define | TEREAD 0x00000000 |
#define | TEWRITE 0x00000002 |
#define | TETAG 0x00000000 |
#define | TEDATA 0x00000004 |
#define | TEDW0 0x00000000 |
#define | TEDW1 0x00000008 |
#define | TEDW2 0x00000010 |
#define | TEDW3 0x00000018 |
#define | TEMB0 0x00000000 |
#define | TEMB1 0x00010000 |
#define | TEMB2 0x00020000 |
#define | TEMB3 0x00030000 |
#define | TESET(x) ((x << 5) & 0x03E0) |
#define | TEWAY0 0x00000000 |
#define | TEWAY1 0x04000000 |
#define | TEWAY2 0x08000000 |
#define | TEWAY3 0x0C000000 |
#define | TEBNKSELA 0x00000000 |
#define | TEBNKSELB 0x00800000 |
#define ACACHE_BCACHE 0x0000000C |
#define ACACHE_BSRAM 0x00000008 |
#define ASRAM_BSRAM 0x00000000 |
#define CPLB_DIRTY 0x00000080 |
#define CPLB_L1_AOW 0x00008000 |
#define CPLB_L1_CHBL 0x00001000 |
#define CPLB_L1SRAM 0x00000020 |
#define CPLB_LOCK 0x00000002 |
#define CPLB_LOCK_P 0x00000001 |
#define CPLB_LRUPRIO 0x00000100 |
#define CPLB_PORTPRIO 0x00000200 |
#define CPLB_SUPV_WR 0x00000010 |
#define CPLB_USER_RD 0x00000004 |
#define CPLB_USER_RD_P 0x00000002 |
#define CPLB_USER_WR 0x00000008 |
#define CPLB_VALID 0x00000001 |
#define CPLB_VALID_P 0x00000000 |
#define CPLB_WT 0x00004000 |
#define DCBS 0x00000010 |
#define DCBS_P 0x04 |
#define DMC0_P 0x02 |
#define DMC1_P 0x03 |
#define DMCTL_DMC0_P DMC0_P |
#define DMCTL_DMC1_P DMC1_P |
#define DMCTL_ENDCPLB_P ENDCPLB_P |
#define DMCTL_ENDM_P ENDM_P |
#define ENDCPLB 0x00000002 |
#define ENDCPLB_P 0x01 |
#define ENDM 0x00000001 |
#define ENDM_P 0x00 |
#define ENICPLB 0x00000002 |
#define ENICPLB_P 0x01 |
#define ENIM 0x00000001 |
#define ENIM_P 0x00 |
#define ILOC0 0x00000008 |
#define ILOC0_P 0x03 |
#define ILOC1 0x00000010 |
#define ILOC1_P 0x04 |
#define ILOC2 0x00000020 |
#define ILOC2_P 0x05 |
#define ILOC3 0x00000040 |
#define ILOC3_P 0x06 |
#define IMC 0x00000004 |
#define IMC_P 0x02 |
#define IMCTL_ENICPLB_P 0x01 |
#define IMCTL_ENIM_P 0x00 |
#define IMCTL_IMC_P 0x02 |
#define LRUPRIORP 0x0D |
#define LRUPRIORST 0x00002000 |
#define PAGE_SIZE_1KB 0x00000000 |
#define PAGE_SIZE_1MB 0x00020000 |
#define PAGE_SIZE_4KB 0x00010000 |
#define PAGE_SIZE_4MB 0x00030000 |
#define PAGE_SIZE_MASK 0x00030000 |
#define PAGE_SIZE_SHIFT 16 |
#define PORT_PREF0 0x00001000 |
#define PORT_PREF0_P 0x12 |
#define PORT_PREF1 0x00002000 |
#define PORT_PREF1_P 0x13 |
#define TEBNKSELA 0x00000000 |
#define TEBNKSELB 0x00800000 |
#define TEDATA 0x00000004 |
#define TEDW0 0x00000000 |
#define TEDW1 0x00000008 |
#define TEDW2 0x00000010 |
#define TEDW3 0x00000018 |
#define TEMB0 0x00000000 |
#define TEMB1 0x00010000 |
#define TEMB2 0x00020000 |
#define TEMB3 0x00030000 |
#define TEREAD 0x00000000 |
#define TESET | ( | x | ) | ((x << 5) & 0x03E0) |
#define TETAG 0x00000000 |
#define TEWAY0 0x00000000 |
#define TEWAY1 0x04000000 |
#define TEWAY2 0x08000000 |
#define TEWAY3 0x0C000000 |
#define TEWRITE 0x00000002 |