inc/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h File Reference


Defines

#define pPLL_CTL   ((uint16_t volatile *)PLL_CTL)
#define bfin_read_PLL_CTL()   bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val)   bfin_write16(PLL_CTL, val)
#define pPLL_DIV   ((uint16_t volatile *)PLL_DIV)
#define bfin_read_PLL_DIV()   bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val)   bfin_write16(PLL_DIV, val)
#define pVR_CTL   ((uint16_t volatile *)VR_CTL)
#define bfin_read_VR_CTL()   bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val)   bfin_write16(VR_CTL, val)
#define pPLL_STAT   ((uint16_t volatile *)PLL_STAT)
#define bfin_read_PLL_STAT()   bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val)   bfin_write16(PLL_STAT, val)
#define pPLL_LOCKCNT   ((uint16_t volatile *)PLL_LOCKCNT)
#define bfin_read_PLL_LOCKCNT()   bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val)   bfin_write16(PLL_LOCKCNT, val)
#define pCHIPID   ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID()   bfin_read32(CHIPID)
#define bfin_write_CHIPID(val)   bfin_write32(CHIPID, val)
#define pSPI_CTL   ((uint16_t volatile *)SPI_CTL)
#define bfin_read_SPI_CTL()   bfin_read16(SPI_CTL)
#define bfin_write_SPI_CTL(val)   bfin_write16(SPI_CTL, val)
#define pSPI_FLG   ((uint16_t volatile *)SPI_FLG)
#define bfin_read_SPI_FLG()   bfin_read16(SPI_FLG)
#define bfin_write_SPI_FLG(val)   bfin_write16(SPI_FLG, val)
#define pSPI_STAT   ((uint16_t volatile *)SPI_STAT)
#define bfin_read_SPI_STAT()   bfin_read16(SPI_STAT)
#define bfin_write_SPI_STAT(val)   bfin_write16(SPI_STAT, val)
#define pSPI_TDBR   ((uint16_t volatile *)SPI_TDBR)
#define bfin_read_SPI_TDBR()   bfin_read16(SPI_TDBR)
#define bfin_write_SPI_TDBR(val)   bfin_write16(SPI_TDBR, val)
#define pSPI_RDBR   ((uint16_t volatile *)SPI_RDBR)
#define bfin_read_SPI_RDBR()   bfin_read16(SPI_RDBR)
#define bfin_write_SPI_RDBR(val)   bfin_write16(SPI_RDBR, val)
#define pSPI_BAUD   ((uint16_t volatile *)SPI_BAUD)
#define bfin_read_SPI_BAUD()   bfin_read16(SPI_BAUD)
#define bfin_write_SPI_BAUD(val)   bfin_write16(SPI_BAUD, val)
#define pSPI_SHADOW   ((uint16_t volatile *)SPI_SHADOW)
#define bfin_read_SPI_SHADOW()   bfin_read16(SPI_SHADOW)
#define bfin_write_SPI_SHADOW(val)   bfin_write16(SPI_SHADOW, val)
#define pWDOGA_CTL   ((uint16_t volatile *)WDOGA_CTL)
#define bfin_read_WDOGA_CTL()   bfin_read16(WDOGA_CTL)
#define bfin_write_WDOGA_CTL(val)   bfin_write16(WDOGA_CTL, val)
#define pWDOGA_CNT   ((uint32_t volatile *)WDOGA_CNT)
#define bfin_read_WDOGA_CNT()   bfin_read32(WDOGA_CNT)
#define bfin_write_WDOGA_CNT(val)   bfin_write32(WDOGA_CNT, val)
#define pWDOGA_STAT   ((uint32_t volatile *)WDOGA_STAT)
#define bfin_read_WDOGA_STAT()   bfin_read32(WDOGA_STAT)
#define bfin_write_WDOGA_STAT(val)   bfin_write32(WDOGA_STAT, val)
#define pWDOGB_CTL   ((uint16_t volatile *)WDOGB_CTL)
#define bfin_read_WDOGB_CTL()   bfin_read16(WDOGB_CTL)
#define bfin_write_WDOGB_CTL(val)   bfin_write16(WDOGB_CTL, val)
#define pWDOGB_CNT   ((uint32_t volatile *)WDOGB_CNT)
#define bfin_read_WDOGB_CNT()   bfin_read32(WDOGB_CNT)
#define bfin_write_WDOGB_CNT(val)   bfin_write32(WDOGB_CNT, val)
#define pWDOGB_STAT   ((uint32_t volatile *)WDOGB_STAT)
#define bfin_read_WDOGB_STAT()   bfin_read32(WDOGB_STAT)
#define bfin_write_WDOGB_STAT(val)   bfin_write32(WDOGB_STAT, val)
#define pDMA1_TC_PER   ((uint16_t volatile *)DMA1_TC_PER)
#define bfin_read_DMA1_TC_PER()   bfin_read16(DMA1_TC_PER)
#define bfin_write_DMA1_TC_PER(val)   bfin_write16(DMA1_TC_PER, val)
#define pDMA1_TC_CNT   ((uint16_t volatile *)DMA1_TC_CNT)
#define bfin_read_DMA1_TC_CNT()   bfin_read16(DMA1_TC_CNT)
#define bfin_write_DMA1_TC_CNT(val)   bfin_write16(DMA1_TC_CNT, val)
#define pDMA1_0_CONFIG   ((uint16_t volatile *)DMA1_0_CONFIG)
#define bfin_read_DMA1_0_CONFIG()   bfin_read16(DMA1_0_CONFIG)
#define bfin_write_DMA1_0_CONFIG(val)   bfin_write16(DMA1_0_CONFIG, val)
#define pDMA1_0_NEXT_DESC_PTR   ((void * volatile *)DMA1_0_NEXT_DESC_PTR)
#define bfin_read_DMA1_0_NEXT_DESC_PTR()   bfin_readPTR(DMA1_0_NEXT_DESC_PTR)
#define bfin_write_DMA1_0_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
#define pDMA1_0_START_ADDR   ((void * volatile *)DMA1_0_START_ADDR)
#define bfin_read_DMA1_0_START_ADDR()   bfin_readPTR(DMA1_0_START_ADDR)
#define bfin_write_DMA1_0_START_ADDR(val)   bfin_writePTR(DMA1_0_START_ADDR, val)
#define pDMA1_0_X_COUNT   ((uint16_t volatile *)DMA1_0_X_COUNT)
#define bfin_read_DMA1_0_X_COUNT()   bfin_read16(DMA1_0_X_COUNT)
#define bfin_write_DMA1_0_X_COUNT(val)   bfin_write16(DMA1_0_X_COUNT, val)
#define pDMA1_0_Y_COUNT   ((uint16_t volatile *)DMA1_0_Y_COUNT)
#define bfin_read_DMA1_0_Y_COUNT()   bfin_read16(DMA1_0_Y_COUNT)
#define bfin_write_DMA1_0_Y_COUNT(val)   bfin_write16(DMA1_0_Y_COUNT, val)
#define pDMA1_0_X_MODIFY   ((uint16_t volatile *)DMA1_0_X_MODIFY)
#define bfin_read_DMA1_0_X_MODIFY()   bfin_read16(DMA1_0_X_MODIFY)
#define bfin_write_DMA1_0_X_MODIFY(val)   bfin_write16(DMA1_0_X_MODIFY, val)
#define pDMA1_0_Y_MODIFY   ((uint16_t volatile *)DMA1_0_Y_MODIFY)
#define bfin_read_DMA1_0_Y_MODIFY()   bfin_read16(DMA1_0_Y_MODIFY)
#define bfin_write_DMA1_0_Y_MODIFY(val)   bfin_write16(DMA1_0_Y_MODIFY, val)
#define pDMA1_0_CURR_DESC_PTR   ((void * volatile *)DMA1_0_CURR_DESC_PTR)
#define bfin_read_DMA1_0_CURR_DESC_PTR()   bfin_readPTR(DMA1_0_CURR_DESC_PTR)
#define bfin_write_DMA1_0_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
#define pDMA1_0_CURR_ADDR   ((void * volatile *)DMA1_0_CURR_ADDR)
#define bfin_read_DMA1_0_CURR_ADDR()   bfin_readPTR(DMA1_0_CURR_ADDR)
#define bfin_write_DMA1_0_CURR_ADDR(val)   bfin_writePTR(DMA1_0_CURR_ADDR, val)
#define pDMA1_0_CURR_X_COUNT   ((uint16_t volatile *)DMA1_0_CURR_X_COUNT)
#define bfin_read_DMA1_0_CURR_X_COUNT()   bfin_read16(DMA1_0_CURR_X_COUNT)
#define bfin_write_DMA1_0_CURR_X_COUNT(val)   bfin_write16(DMA1_0_CURR_X_COUNT, val)
#define pDMA1_0_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT)
#define bfin_read_DMA1_0_CURR_Y_COUNT()   bfin_read16(DMA1_0_CURR_Y_COUNT)
#define bfin_write_DMA1_0_CURR_Y_COUNT(val)   bfin_write16(DMA1_0_CURR_Y_COUNT, val)
#define pDMA1_0_IRQ_STATUS   ((uint16_t volatile *)DMA1_0_IRQ_STATUS)
#define bfin_read_DMA1_0_IRQ_STATUS()   bfin_read16(DMA1_0_IRQ_STATUS)
#define bfin_write_DMA1_0_IRQ_STATUS(val)   bfin_write16(DMA1_0_IRQ_STATUS, val)
#define pDMA1_0_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP)
#define bfin_read_DMA1_0_PERIPHERAL_MAP()   bfin_read16(DMA1_0_PERIPHERAL_MAP)
#define bfin_write_DMA1_0_PERIPHERAL_MAP(val)   bfin_write16(DMA1_0_PERIPHERAL_MAP, val)
#define pDMA1_1_CONFIG   ((uint16_t volatile *)DMA1_1_CONFIG)
#define bfin_read_DMA1_1_CONFIG()   bfin_read16(DMA1_1_CONFIG)
#define bfin_write_DMA1_1_CONFIG(val)   bfin_write16(DMA1_1_CONFIG, val)
#define pDMA1_1_NEXT_DESC_PTR   ((void * volatile *)DMA1_1_NEXT_DESC_PTR)
#define bfin_read_DMA1_1_NEXT_DESC_PTR()   bfin_readPTR(DMA1_1_NEXT_DESC_PTR)
#define bfin_write_DMA1_1_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
#define pDMA1_1_START_ADDR   ((void * volatile *)DMA1_1_START_ADDR)
#define bfin_read_DMA1_1_START_ADDR()   bfin_readPTR(DMA1_1_START_ADDR)
#define bfin_write_DMA1_1_START_ADDR(val)   bfin_writePTR(DMA1_1_START_ADDR, val)
#define pDMA1_1_X_COUNT   ((uint16_t volatile *)DMA1_1_X_COUNT)
#define bfin_read_DMA1_1_X_COUNT()   bfin_read16(DMA1_1_X_COUNT)
#define bfin_write_DMA1_1_X_COUNT(val)   bfin_write16(DMA1_1_X_COUNT, val)
#define pDMA1_1_Y_COUNT   ((uint16_t volatile *)DMA1_1_Y_COUNT)
#define bfin_read_DMA1_1_Y_COUNT()   bfin_read16(DMA1_1_Y_COUNT)
#define bfin_write_DMA1_1_Y_COUNT(val)   bfin_write16(DMA1_1_Y_COUNT, val)
#define pDMA1_1_X_MODIFY   ((uint16_t volatile *)DMA1_1_X_MODIFY)
#define bfin_read_DMA1_1_X_MODIFY()   bfin_read16(DMA1_1_X_MODIFY)
#define bfin_write_DMA1_1_X_MODIFY(val)   bfin_write16(DMA1_1_X_MODIFY, val)
#define pDMA1_1_Y_MODIFY   ((uint16_t volatile *)DMA1_1_Y_MODIFY)
#define bfin_read_DMA1_1_Y_MODIFY()   bfin_read16(DMA1_1_Y_MODIFY)
#define bfin_write_DMA1_1_Y_MODIFY(val)   bfin_write16(DMA1_1_Y_MODIFY, val)
#define pDMA1_1_CURR_DESC_PTR   ((void * volatile *)DMA1_1_CURR_DESC_PTR)
#define bfin_read_DMA1_1_CURR_DESC_PTR()   bfin_readPTR(DMA1_1_CURR_DESC_PTR)
#define bfin_write_DMA1_1_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
#define pDMA1_1_CURR_ADDR   ((void * volatile *)DMA1_1_CURR_ADDR)
#define bfin_read_DMA1_1_CURR_ADDR()   bfin_readPTR(DMA1_1_CURR_ADDR)
#define bfin_write_DMA1_1_CURR_ADDR(val)   bfin_writePTR(DMA1_1_CURR_ADDR, val)
#define pDMA1_1_CURR_X_COUNT   ((uint16_t volatile *)DMA1_1_CURR_X_COUNT)
#define bfin_read_DMA1_1_CURR_X_COUNT()   bfin_read16(DMA1_1_CURR_X_COUNT)
#define bfin_write_DMA1_1_CURR_X_COUNT(val)   bfin_write16(DMA1_1_CURR_X_COUNT, val)
#define pDMA1_1_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT)
#define bfin_read_DMA1_1_CURR_Y_COUNT()   bfin_read16(DMA1_1_CURR_Y_COUNT)
#define bfin_write_DMA1_1_CURR_Y_COUNT(val)   bfin_write16(DMA1_1_CURR_Y_COUNT, val)
#define pDMA1_1_IRQ_STATUS   ((uint16_t volatile *)DMA1_1_IRQ_STATUS)
#define bfin_read_DMA1_1_IRQ_STATUS()   bfin_read16(DMA1_1_IRQ_STATUS)
#define bfin_write_DMA1_1_IRQ_STATUS(val)   bfin_write16(DMA1_1_IRQ_STATUS, val)
#define pDMA1_1_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP)
#define bfin_read_DMA1_1_PERIPHERAL_MAP()   bfin_read16(DMA1_1_PERIPHERAL_MAP)
#define bfin_write_DMA1_1_PERIPHERAL_MAP(val)   bfin_write16(DMA1_1_PERIPHERAL_MAP, val)
#define pDMA1_2_CONFIG   ((uint16_t volatile *)DMA1_2_CONFIG)
#define bfin_read_DMA1_2_CONFIG()   bfin_read16(DMA1_2_CONFIG)
#define bfin_write_DMA1_2_CONFIG(val)   bfin_write16(DMA1_2_CONFIG, val)
#define pDMA1_2_NEXT_DESC_PTR   ((void * volatile *)DMA1_2_NEXT_DESC_PTR)
#define bfin_read_DMA1_2_NEXT_DESC_PTR()   bfin_readPTR(DMA1_2_NEXT_DESC_PTR)
#define bfin_write_DMA1_2_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
#define pDMA1_2_START_ADDR   ((void * volatile *)DMA1_2_START_ADDR)
#define bfin_read_DMA1_2_START_ADDR()   bfin_readPTR(DMA1_2_START_ADDR)
#define bfin_write_DMA1_2_START_ADDR(val)   bfin_writePTR(DMA1_2_START_ADDR, val)
#define pDMA1_2_X_COUNT   ((uint16_t volatile *)DMA1_2_X_COUNT)
#define bfin_read_DMA1_2_X_COUNT()   bfin_read16(DMA1_2_X_COUNT)
#define bfin_write_DMA1_2_X_COUNT(val)   bfin_write16(DMA1_2_X_COUNT, val)
#define pDMA1_2_Y_COUNT   ((uint16_t volatile *)DMA1_2_Y_COUNT)
#define bfin_read_DMA1_2_Y_COUNT()   bfin_read16(DMA1_2_Y_COUNT)
#define bfin_write_DMA1_2_Y_COUNT(val)   bfin_write16(DMA1_2_Y_COUNT, val)
#define pDMA1_2_X_MODIFY   ((uint16_t volatile *)DMA1_2_X_MODIFY)
#define bfin_read_DMA1_2_X_MODIFY()   bfin_read16(DMA1_2_X_MODIFY)
#define bfin_write_DMA1_2_X_MODIFY(val)   bfin_write16(DMA1_2_X_MODIFY, val)
#define pDMA1_2_Y_MODIFY   ((uint16_t volatile *)DMA1_2_Y_MODIFY)
#define bfin_read_DMA1_2_Y_MODIFY()   bfin_read16(DMA1_2_Y_MODIFY)
#define bfin_write_DMA1_2_Y_MODIFY(val)   bfin_write16(DMA1_2_Y_MODIFY, val)
#define pDMA1_2_CURR_DESC_PTR   ((void * volatile *)DMA1_2_CURR_DESC_PTR)
#define bfin_read_DMA1_2_CURR_DESC_PTR()   bfin_readPTR(DMA1_2_CURR_DESC_PTR)
#define bfin_write_DMA1_2_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
#define pDMA1_2_CURR_ADDR   ((void * volatile *)DMA1_2_CURR_ADDR)
#define bfin_read_DMA1_2_CURR_ADDR()   bfin_readPTR(DMA1_2_CURR_ADDR)
#define bfin_write_DMA1_2_CURR_ADDR(val)   bfin_writePTR(DMA1_2_CURR_ADDR, val)
#define pDMA1_2_CURR_X_COUNT   ((uint16_t volatile *)DMA1_2_CURR_X_COUNT)
#define bfin_read_DMA1_2_CURR_X_COUNT()   bfin_read16(DMA1_2_CURR_X_COUNT)
#define bfin_write_DMA1_2_CURR_X_COUNT(val)   bfin_write16(DMA1_2_CURR_X_COUNT, val)
#define pDMA1_2_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT)
#define bfin_read_DMA1_2_CURR_Y_COUNT()   bfin_read16(DMA1_2_CURR_Y_COUNT)
#define bfin_write_DMA1_2_CURR_Y_COUNT(val)   bfin_write16(DMA1_2_CURR_Y_COUNT, val)
#define pDMA1_2_IRQ_STATUS   ((uint16_t volatile *)DMA1_2_IRQ_STATUS)
#define bfin_read_DMA1_2_IRQ_STATUS()   bfin_read16(DMA1_2_IRQ_STATUS)
#define bfin_write_DMA1_2_IRQ_STATUS(val)   bfin_write16(DMA1_2_IRQ_STATUS, val)
#define pDMA1_2_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP)
#define bfin_read_DMA1_2_PERIPHERAL_MAP()   bfin_read16(DMA1_2_PERIPHERAL_MAP)
#define bfin_write_DMA1_2_PERIPHERAL_MAP(val)   bfin_write16(DMA1_2_PERIPHERAL_MAP, val)
#define pDMA1_3_CONFIG   ((uint16_t volatile *)DMA1_3_CONFIG)
#define bfin_read_DMA1_3_CONFIG()   bfin_read16(DMA1_3_CONFIG)
#define bfin_write_DMA1_3_CONFIG(val)   bfin_write16(DMA1_3_CONFIG, val)
#define pDMA1_3_NEXT_DESC_PTR   ((void * volatile *)DMA1_3_NEXT_DESC_PTR)
#define bfin_read_DMA1_3_NEXT_DESC_PTR()   bfin_readPTR(DMA1_3_NEXT_DESC_PTR)
#define bfin_write_DMA1_3_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
#define pDMA1_3_START_ADDR   ((void * volatile *)DMA1_3_START_ADDR)
#define bfin_read_DMA1_3_START_ADDR()   bfin_readPTR(DMA1_3_START_ADDR)
#define bfin_write_DMA1_3_START_ADDR(val)   bfin_writePTR(DMA1_3_START_ADDR, val)
#define pDMA1_3_X_COUNT   ((uint16_t volatile *)DMA1_3_X_COUNT)
#define bfin_read_DMA1_3_X_COUNT()   bfin_read16(DMA1_3_X_COUNT)
#define bfin_write_DMA1_3_X_COUNT(val)   bfin_write16(DMA1_3_X_COUNT, val)
#define pDMA1_3_Y_COUNT   ((uint16_t volatile *)DMA1_3_Y_COUNT)
#define bfin_read_DMA1_3_Y_COUNT()   bfin_read16(DMA1_3_Y_COUNT)
#define bfin_write_DMA1_3_Y_COUNT(val)   bfin_write16(DMA1_3_Y_COUNT, val)
#define pDMA1_3_X_MODIFY   ((uint16_t volatile *)DMA1_3_X_MODIFY)
#define bfin_read_DMA1_3_X_MODIFY()   bfin_read16(DMA1_3_X_MODIFY)
#define bfin_write_DMA1_3_X_MODIFY(val)   bfin_write16(DMA1_3_X_MODIFY, val)
#define pDMA1_3_Y_MODIFY   ((uint16_t volatile *)DMA1_3_Y_MODIFY)
#define bfin_read_DMA1_3_Y_MODIFY()   bfin_read16(DMA1_3_Y_MODIFY)
#define bfin_write_DMA1_3_Y_MODIFY(val)   bfin_write16(DMA1_3_Y_MODIFY, val)
#define pDMA1_3_CURR_DESC_PTR   ((void * volatile *)DMA1_3_CURR_DESC_PTR)
#define bfin_read_DMA1_3_CURR_DESC_PTR()   bfin_readPTR(DMA1_3_CURR_DESC_PTR)
#define bfin_write_DMA1_3_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
#define pDMA1_3_CURR_ADDR   ((void * volatile *)DMA1_3_CURR_ADDR)
#define bfin_read_DMA1_3_CURR_ADDR()   bfin_readPTR(DMA1_3_CURR_ADDR)
#define bfin_write_DMA1_3_CURR_ADDR(val)   bfin_writePTR(DMA1_3_CURR_ADDR, val)
#define pDMA1_3_CURR_X_COUNT   ((uint16_t volatile *)DMA1_3_CURR_X_COUNT)
#define bfin_read_DMA1_3_CURR_X_COUNT()   bfin_read16(DMA1_3_CURR_X_COUNT)
#define bfin_write_DMA1_3_CURR_X_COUNT(val)   bfin_write16(DMA1_3_CURR_X_COUNT, val)
#define pDMA1_3_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT)
#define bfin_read_DMA1_3_CURR_Y_COUNT()   bfin_read16(DMA1_3_CURR_Y_COUNT)
#define bfin_write_DMA1_3_CURR_Y_COUNT(val)   bfin_write16(DMA1_3_CURR_Y_COUNT, val)
#define pDMA1_3_IRQ_STATUS   ((uint16_t volatile *)DMA1_3_IRQ_STATUS)
#define bfin_read_DMA1_3_IRQ_STATUS()   bfin_read16(DMA1_3_IRQ_STATUS)
#define bfin_write_DMA1_3_IRQ_STATUS(val)   bfin_write16(DMA1_3_IRQ_STATUS, val)
#define pDMA1_3_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP)
#define bfin_read_DMA1_3_PERIPHERAL_MAP()   bfin_read16(DMA1_3_PERIPHERAL_MAP)
#define bfin_write_DMA1_3_PERIPHERAL_MAP(val)   bfin_write16(DMA1_3_PERIPHERAL_MAP, val)
#define pDMA1_4_CONFIG   ((uint16_t volatile *)DMA1_4_CONFIG)
#define bfin_read_DMA1_4_CONFIG()   bfin_read16(DMA1_4_CONFIG)
#define bfin_write_DMA1_4_CONFIG(val)   bfin_write16(DMA1_4_CONFIG, val)
#define pDMA1_4_NEXT_DESC_PTR   ((void * volatile *)DMA1_4_NEXT_DESC_PTR)
#define bfin_read_DMA1_4_NEXT_DESC_PTR()   bfin_readPTR(DMA1_4_NEXT_DESC_PTR)
#define bfin_write_DMA1_4_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
#define pDMA1_4_START_ADDR   ((void * volatile *)DMA1_4_START_ADDR)
#define bfin_read_DMA1_4_START_ADDR()   bfin_readPTR(DMA1_4_START_ADDR)
#define bfin_write_DMA1_4_START_ADDR(val)   bfin_writePTR(DMA1_4_START_ADDR, val)
#define pDMA1_4_X_COUNT   ((uint16_t volatile *)DMA1_4_X_COUNT)
#define bfin_read_DMA1_4_X_COUNT()   bfin_read16(DMA1_4_X_COUNT)
#define bfin_write_DMA1_4_X_COUNT(val)   bfin_write16(DMA1_4_X_COUNT, val)
#define pDMA1_4_Y_COUNT   ((uint16_t volatile *)DMA1_4_Y_COUNT)
#define bfin_read_DMA1_4_Y_COUNT()   bfin_read16(DMA1_4_Y_COUNT)
#define bfin_write_DMA1_4_Y_COUNT(val)   bfin_write16(DMA1_4_Y_COUNT, val)
#define pDMA1_4_X_MODIFY   ((uint16_t volatile *)DMA1_4_X_MODIFY)
#define bfin_read_DMA1_4_X_MODIFY()   bfin_read16(DMA1_4_X_MODIFY)
#define bfin_write_DMA1_4_X_MODIFY(val)   bfin_write16(DMA1_4_X_MODIFY, val)
#define pDMA1_4_Y_MODIFY   ((uint16_t volatile *)DMA1_4_Y_MODIFY)
#define bfin_read_DMA1_4_Y_MODIFY()   bfin_read16(DMA1_4_Y_MODIFY)
#define bfin_write_DMA1_4_Y_MODIFY(val)   bfin_write16(DMA1_4_Y_MODIFY, val)
#define pDMA1_4_CURR_DESC_PTR   ((void * volatile *)DMA1_4_CURR_DESC_PTR)
#define bfin_read_DMA1_4_CURR_DESC_PTR()   bfin_readPTR(DMA1_4_CURR_DESC_PTR)
#define bfin_write_DMA1_4_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
#define pDMA1_4_CURR_ADDR   ((void * volatile *)DMA1_4_CURR_ADDR)
#define bfin_read_DMA1_4_CURR_ADDR()   bfin_readPTR(DMA1_4_CURR_ADDR)
#define bfin_write_DMA1_4_CURR_ADDR(val)   bfin_writePTR(DMA1_4_CURR_ADDR, val)
#define pDMA1_4_CURR_X_COUNT   ((uint16_t volatile *)DMA1_4_CURR_X_COUNT)
#define bfin_read_DMA1_4_CURR_X_COUNT()   bfin_read16(DMA1_4_CURR_X_COUNT)
#define bfin_write_DMA1_4_CURR_X_COUNT(val)   bfin_write16(DMA1_4_CURR_X_COUNT, val)
#define pDMA1_4_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT)
#define bfin_read_DMA1_4_CURR_Y_COUNT()   bfin_read16(DMA1_4_CURR_Y_COUNT)
#define bfin_write_DMA1_4_CURR_Y_COUNT(val)   bfin_write16(DMA1_4_CURR_Y_COUNT, val)
#define pDMA1_4_IRQ_STATUS   ((uint16_t volatile *)DMA1_4_IRQ_STATUS)
#define bfin_read_DMA1_4_IRQ_STATUS()   bfin_read16(DMA1_4_IRQ_STATUS)
#define bfin_write_DMA1_4_IRQ_STATUS(val)   bfin_write16(DMA1_4_IRQ_STATUS, val)
#define pDMA1_4_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP)
#define bfin_read_DMA1_4_PERIPHERAL_MAP()   bfin_read16(DMA1_4_PERIPHERAL_MAP)
#define bfin_write_DMA1_4_PERIPHERAL_MAP(val)   bfin_write16(DMA1_4_PERIPHERAL_MAP, val)
#define pDMA1_5_CONFIG   ((uint16_t volatile *)DMA1_5_CONFIG)
#define bfin_read_DMA1_5_CONFIG()   bfin_read16(DMA1_5_CONFIG)
#define bfin_write_DMA1_5_CONFIG(val)   bfin_write16(DMA1_5_CONFIG, val)
#define pDMA1_5_NEXT_DESC_PTR   ((void * volatile *)DMA1_5_NEXT_DESC_PTR)
#define bfin_read_DMA1_5_NEXT_DESC_PTR()   bfin_readPTR(DMA1_5_NEXT_DESC_PTR)
#define bfin_write_DMA1_5_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
#define pDMA1_5_START_ADDR   ((void * volatile *)DMA1_5_START_ADDR)
#define bfin_read_DMA1_5_START_ADDR()   bfin_readPTR(DMA1_5_START_ADDR)
#define bfin_write_DMA1_5_START_ADDR(val)   bfin_writePTR(DMA1_5_START_ADDR, val)
#define pDMA1_5_X_COUNT   ((uint16_t volatile *)DMA1_5_X_COUNT)
#define bfin_read_DMA1_5_X_COUNT()   bfin_read16(DMA1_5_X_COUNT)
#define bfin_write_DMA1_5_X_COUNT(val)   bfin_write16(DMA1_5_X_COUNT, val)
#define pDMA1_5_Y_COUNT   ((uint16_t volatile *)DMA1_5_Y_COUNT)
#define bfin_read_DMA1_5_Y_COUNT()   bfin_read16(DMA1_5_Y_COUNT)
#define bfin_write_DMA1_5_Y_COUNT(val)   bfin_write16(DMA1_5_Y_COUNT, val)
#define pDMA1_5_X_MODIFY   ((uint16_t volatile *)DMA1_5_X_MODIFY)
#define bfin_read_DMA1_5_X_MODIFY()   bfin_read16(DMA1_5_X_MODIFY)
#define bfin_write_DMA1_5_X_MODIFY(val)   bfin_write16(DMA1_5_X_MODIFY, val)
#define pDMA1_5_Y_MODIFY   ((uint16_t volatile *)DMA1_5_Y_MODIFY)
#define bfin_read_DMA1_5_Y_MODIFY()   bfin_read16(DMA1_5_Y_MODIFY)
#define bfin_write_DMA1_5_Y_MODIFY(val)   bfin_write16(DMA1_5_Y_MODIFY, val)
#define pDMA1_5_CURR_DESC_PTR   ((void * volatile *)DMA1_5_CURR_DESC_PTR)
#define bfin_read_DMA1_5_CURR_DESC_PTR()   bfin_readPTR(DMA1_5_CURR_DESC_PTR)
#define bfin_write_DMA1_5_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
#define pDMA1_5_CURR_ADDR   ((void * volatile *)DMA1_5_CURR_ADDR)
#define bfin_read_DMA1_5_CURR_ADDR()   bfin_readPTR(DMA1_5_CURR_ADDR)
#define bfin_write_DMA1_5_CURR_ADDR(val)   bfin_writePTR(DMA1_5_CURR_ADDR, val)
#define pDMA1_5_CURR_X_COUNT   ((uint16_t volatile *)DMA1_5_CURR_X_COUNT)
#define bfin_read_DMA1_5_CURR_X_COUNT()   bfin_read16(DMA1_5_CURR_X_COUNT)
#define bfin_write_DMA1_5_CURR_X_COUNT(val)   bfin_write16(DMA1_5_CURR_X_COUNT, val)
#define pDMA1_5_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT)
#define bfin_read_DMA1_5_CURR_Y_COUNT()   bfin_read16(DMA1_5_CURR_Y_COUNT)
#define bfin_write_DMA1_5_CURR_Y_COUNT(val)   bfin_write16(DMA1_5_CURR_Y_COUNT, val)
#define pDMA1_5_IRQ_STATUS   ((uint16_t volatile *)DMA1_5_IRQ_STATUS)
#define bfin_read_DMA1_5_IRQ_STATUS()   bfin_read16(DMA1_5_IRQ_STATUS)
#define bfin_write_DMA1_5_IRQ_STATUS(val)   bfin_write16(DMA1_5_IRQ_STATUS, val)
#define pDMA1_5_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP)
#define bfin_read_DMA1_5_PERIPHERAL_MAP()   bfin_read16(DMA1_5_PERIPHERAL_MAP)
#define bfin_write_DMA1_5_PERIPHERAL_MAP(val)   bfin_write16(DMA1_5_PERIPHERAL_MAP, val)
#define pDMA1_6_CONFIG   ((uint16_t volatile *)DMA1_6_CONFIG)
#define bfin_read_DMA1_6_CONFIG()   bfin_read16(DMA1_6_CONFIG)
#define bfin_write_DMA1_6_CONFIG(val)   bfin_write16(DMA1_6_CONFIG, val)
#define pDMA1_6_NEXT_DESC_PTR   ((void * volatile *)DMA1_6_NEXT_DESC_PTR)
#define bfin_read_DMA1_6_NEXT_DESC_PTR()   bfin_readPTR(DMA1_6_NEXT_DESC_PTR)
#define bfin_write_DMA1_6_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
#define pDMA1_6_START_ADDR   ((void * volatile *)DMA1_6_START_ADDR)
#define bfin_read_DMA1_6_START_ADDR()   bfin_readPTR(DMA1_6_START_ADDR)
#define bfin_write_DMA1_6_START_ADDR(val)   bfin_writePTR(DMA1_6_START_ADDR, val)
#define pDMA1_6_X_COUNT   ((uint16_t volatile *)DMA1_6_X_COUNT)
#define bfin_read_DMA1_6_X_COUNT()   bfin_read16(DMA1_6_X_COUNT)
#define bfin_write_DMA1_6_X_COUNT(val)   bfin_write16(DMA1_6_X_COUNT, val)
#define pDMA1_6_Y_COUNT   ((uint16_t volatile *)DMA1_6_Y_COUNT)
#define bfin_read_DMA1_6_Y_COUNT()   bfin_read16(DMA1_6_Y_COUNT)
#define bfin_write_DMA1_6_Y_COUNT(val)   bfin_write16(DMA1_6_Y_COUNT, val)
#define pDMA1_6_X_MODIFY   ((uint16_t volatile *)DMA1_6_X_MODIFY)
#define bfin_read_DMA1_6_X_MODIFY()   bfin_read16(DMA1_6_X_MODIFY)
#define bfin_write_DMA1_6_X_MODIFY(val)   bfin_write16(DMA1_6_X_MODIFY, val)
#define pDMA1_6_Y_MODIFY   ((uint16_t volatile *)DMA1_6_Y_MODIFY)
#define bfin_read_DMA1_6_Y_MODIFY()   bfin_read16(DMA1_6_Y_MODIFY)
#define bfin_write_DMA1_6_Y_MODIFY(val)   bfin_write16(DMA1_6_Y_MODIFY, val)
#define pDMA1_6_CURR_DESC_PTR   ((void * volatile *)DMA1_6_CURR_DESC_PTR)
#define bfin_read_DMA1_6_CURR_DESC_PTR()   bfin_readPTR(DMA1_6_CURR_DESC_PTR)
#define bfin_write_DMA1_6_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
#define pDMA1_6_CURR_ADDR   ((void * volatile *)DMA1_6_CURR_ADDR)
#define bfin_read_DMA1_6_CURR_ADDR()   bfin_readPTR(DMA1_6_CURR_ADDR)
#define bfin_write_DMA1_6_CURR_ADDR(val)   bfin_writePTR(DMA1_6_CURR_ADDR, val)
#define pDMA1_6_CURR_X_COUNT   ((uint16_t volatile *)DMA1_6_CURR_X_COUNT)
#define bfin_read_DMA1_6_CURR_X_COUNT()   bfin_read16(DMA1_6_CURR_X_COUNT)
#define bfin_write_DMA1_6_CURR_X_COUNT(val)   bfin_write16(DMA1_6_CURR_X_COUNT, val)
#define pDMA1_6_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT)
#define bfin_read_DMA1_6_CURR_Y_COUNT()   bfin_read16(DMA1_6_CURR_Y_COUNT)
#define bfin_write_DMA1_6_CURR_Y_COUNT(val)   bfin_write16(DMA1_6_CURR_Y_COUNT, val)
#define pDMA1_6_IRQ_STATUS   ((uint16_t volatile *)DMA1_6_IRQ_STATUS)
#define bfin_read_DMA1_6_IRQ_STATUS()   bfin_read16(DMA1_6_IRQ_STATUS)
#define bfin_write_DMA1_6_IRQ_STATUS(val)   bfin_write16(DMA1_6_IRQ_STATUS, val)
#define pDMA1_6_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP)
#define bfin_read_DMA1_6_PERIPHERAL_MAP()   bfin_read16(DMA1_6_PERIPHERAL_MAP)
#define bfin_write_DMA1_6_PERIPHERAL_MAP(val)   bfin_write16(DMA1_6_PERIPHERAL_MAP, val)
#define pDMA1_7_CONFIG   ((uint16_t volatile *)DMA1_7_CONFIG)
#define bfin_read_DMA1_7_CONFIG()   bfin_read16(DMA1_7_CONFIG)
#define bfin_write_DMA1_7_CONFIG(val)   bfin_write16(DMA1_7_CONFIG, val)
#define pDMA1_7_NEXT_DESC_PTR   ((void * volatile *)DMA1_7_NEXT_DESC_PTR)
#define bfin_read_DMA1_7_NEXT_DESC_PTR()   bfin_readPTR(DMA1_7_NEXT_DESC_PTR)
#define bfin_write_DMA1_7_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
#define pDMA1_7_START_ADDR   ((void * volatile *)DMA1_7_START_ADDR)
#define bfin_read_DMA1_7_START_ADDR()   bfin_readPTR(DMA1_7_START_ADDR)
#define bfin_write_DMA1_7_START_ADDR(val)   bfin_writePTR(DMA1_7_START_ADDR, val)
#define pDMA1_7_X_COUNT   ((uint16_t volatile *)DMA1_7_X_COUNT)
#define bfin_read_DMA1_7_X_COUNT()   bfin_read16(DMA1_7_X_COUNT)
#define bfin_write_DMA1_7_X_COUNT(val)   bfin_write16(DMA1_7_X_COUNT, val)
#define pDMA1_7_Y_COUNT   ((uint16_t volatile *)DMA1_7_Y_COUNT)
#define bfin_read_DMA1_7_Y_COUNT()   bfin_read16(DMA1_7_Y_COUNT)
#define bfin_write_DMA1_7_Y_COUNT(val)   bfin_write16(DMA1_7_Y_COUNT, val)
#define pDMA1_7_X_MODIFY   ((uint16_t volatile *)DMA1_7_X_MODIFY)
#define bfin_read_DMA1_7_X_MODIFY()   bfin_read16(DMA1_7_X_MODIFY)
#define bfin_write_DMA1_7_X_MODIFY(val)   bfin_write16(DMA1_7_X_MODIFY, val)
#define pDMA1_7_Y_MODIFY   ((uint16_t volatile *)DMA1_7_Y_MODIFY)
#define bfin_read_DMA1_7_Y_MODIFY()   bfin_read16(DMA1_7_Y_MODIFY)
#define bfin_write_DMA1_7_Y_MODIFY(val)   bfin_write16(DMA1_7_Y_MODIFY, val)
#define pDMA1_7_CURR_DESC_PTR   ((void * volatile *)DMA1_7_CURR_DESC_PTR)
#define bfin_read_DMA1_7_CURR_DESC_PTR()   bfin_readPTR(DMA1_7_CURR_DESC_PTR)
#define bfin_write_DMA1_7_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
#define pDMA1_7_CURR_ADDR   ((void * volatile *)DMA1_7_CURR_ADDR)
#define bfin_read_DMA1_7_CURR_ADDR()   bfin_readPTR(DMA1_7_CURR_ADDR)
#define bfin_write_DMA1_7_CURR_ADDR(val)   bfin_writePTR(DMA1_7_CURR_ADDR, val)
#define pDMA1_7_CURR_X_COUNT   ((uint16_t volatile *)DMA1_7_CURR_X_COUNT)
#define bfin_read_DMA1_7_CURR_X_COUNT()   bfin_read16(DMA1_7_CURR_X_COUNT)
#define bfin_write_DMA1_7_CURR_X_COUNT(val)   bfin_write16(DMA1_7_CURR_X_COUNT, val)
#define pDMA1_7_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT)
#define bfin_read_DMA1_7_CURR_Y_COUNT()   bfin_read16(DMA1_7_CURR_Y_COUNT)
#define bfin_write_DMA1_7_CURR_Y_COUNT(val)   bfin_write16(DMA1_7_CURR_Y_COUNT, val)
#define pDMA1_7_IRQ_STATUS   ((uint16_t volatile *)DMA1_7_IRQ_STATUS)
#define bfin_read_DMA1_7_IRQ_STATUS()   bfin_read16(DMA1_7_IRQ_STATUS)
#define bfin_write_DMA1_7_IRQ_STATUS(val)   bfin_write16(DMA1_7_IRQ_STATUS, val)
#define pDMA1_7_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP)
#define bfin_read_DMA1_7_PERIPHERAL_MAP()   bfin_read16(DMA1_7_PERIPHERAL_MAP)
#define bfin_write_DMA1_7_PERIPHERAL_MAP(val)   bfin_write16(DMA1_7_PERIPHERAL_MAP, val)
#define pDMA1_8_CONFIG   ((uint16_t volatile *)DMA1_8_CONFIG)
#define bfin_read_DMA1_8_CONFIG()   bfin_read16(DMA1_8_CONFIG)
#define bfin_write_DMA1_8_CONFIG(val)   bfin_write16(DMA1_8_CONFIG, val)
#define pDMA1_8_NEXT_DESC_PTR   ((void * volatile *)DMA1_8_NEXT_DESC_PTR)
#define bfin_read_DMA1_8_NEXT_DESC_PTR()   bfin_readPTR(DMA1_8_NEXT_DESC_PTR)
#define bfin_write_DMA1_8_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
#define pDMA1_8_START_ADDR   ((void * volatile *)DMA1_8_START_ADDR)
#define bfin_read_DMA1_8_START_ADDR()   bfin_readPTR(DMA1_8_START_ADDR)
#define bfin_write_DMA1_8_START_ADDR(val)   bfin_writePTR(DMA1_8_START_ADDR, val)
#define pDMA1_8_X_COUNT   ((uint16_t volatile *)DMA1_8_X_COUNT)
#define bfin_read_DMA1_8_X_COUNT()   bfin_read16(DMA1_8_X_COUNT)
#define bfin_write_DMA1_8_X_COUNT(val)   bfin_write16(DMA1_8_X_COUNT, val)
#define pDMA1_8_Y_COUNT   ((uint16_t volatile *)DMA1_8_Y_COUNT)
#define bfin_read_DMA1_8_Y_COUNT()   bfin_read16(DMA1_8_Y_COUNT)
#define bfin_write_DMA1_8_Y_COUNT(val)   bfin_write16(DMA1_8_Y_COUNT, val)
#define pDMA1_8_X_MODIFY   ((uint16_t volatile *)DMA1_8_X_MODIFY)
#define bfin_read_DMA1_8_X_MODIFY()   bfin_read16(DMA1_8_X_MODIFY)
#define bfin_write_DMA1_8_X_MODIFY(val)   bfin_write16(DMA1_8_X_MODIFY, val)
#define pDMA1_8_Y_MODIFY   ((uint16_t volatile *)DMA1_8_Y_MODIFY)
#define bfin_read_DMA1_8_Y_MODIFY()   bfin_read16(DMA1_8_Y_MODIFY)
#define bfin_write_DMA1_8_Y_MODIFY(val)   bfin_write16(DMA1_8_Y_MODIFY, val)
#define pDMA1_8_CURR_DESC_PTR   ((void * volatile *)DMA1_8_CURR_DESC_PTR)
#define bfin_read_DMA1_8_CURR_DESC_PTR()   bfin_readPTR(DMA1_8_CURR_DESC_PTR)
#define bfin_write_DMA1_8_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
#define pDMA1_8_CURR_ADDR   ((void * volatile *)DMA1_8_CURR_ADDR)
#define bfin_read_DMA1_8_CURR_ADDR()   bfin_readPTR(DMA1_8_CURR_ADDR)
#define bfin_write_DMA1_8_CURR_ADDR(val)   bfin_writePTR(DMA1_8_CURR_ADDR, val)
#define pDMA1_8_CURR_X_COUNT   ((uint16_t volatile *)DMA1_8_CURR_X_COUNT)
#define bfin_read_DMA1_8_CURR_X_COUNT()   bfin_read16(DMA1_8_CURR_X_COUNT)
#define bfin_write_DMA1_8_CURR_X_COUNT(val)   bfin_write16(DMA1_8_CURR_X_COUNT, val)
#define pDMA1_8_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT)
#define bfin_read_DMA1_8_CURR_Y_COUNT()   bfin_read16(DMA1_8_CURR_Y_COUNT)
#define bfin_write_DMA1_8_CURR_Y_COUNT(val)   bfin_write16(DMA1_8_CURR_Y_COUNT, val)
#define pDMA1_8_IRQ_STATUS   ((uint16_t volatile *)DMA1_8_IRQ_STATUS)
#define bfin_read_DMA1_8_IRQ_STATUS()   bfin_read16(DMA1_8_IRQ_STATUS)
#define bfin_write_DMA1_8_IRQ_STATUS(val)   bfin_write16(DMA1_8_IRQ_STATUS, val)
#define pDMA1_8_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP)
#define bfin_read_DMA1_8_PERIPHERAL_MAP()   bfin_read16(DMA1_8_PERIPHERAL_MAP)
#define bfin_write_DMA1_8_PERIPHERAL_MAP(val)   bfin_write16(DMA1_8_PERIPHERAL_MAP, val)
#define pDMA1_9_CONFIG   ((uint16_t volatile *)DMA1_9_CONFIG)
#define bfin_read_DMA1_9_CONFIG()   bfin_read16(DMA1_9_CONFIG)
#define bfin_write_DMA1_9_CONFIG(val)   bfin_write16(DMA1_9_CONFIG, val)
#define pDMA1_9_NEXT_DESC_PTR   ((void * volatile *)DMA1_9_NEXT_DESC_PTR)
#define bfin_read_DMA1_9_NEXT_DESC_PTR()   bfin_readPTR(DMA1_9_NEXT_DESC_PTR)
#define bfin_write_DMA1_9_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
#define pDMA1_9_START_ADDR   ((void * volatile *)DMA1_9_START_ADDR)
#define bfin_read_DMA1_9_START_ADDR()   bfin_readPTR(DMA1_9_START_ADDR)
#define bfin_write_DMA1_9_START_ADDR(val)   bfin_writePTR(DMA1_9_START_ADDR, val)
#define pDMA1_9_X_COUNT   ((uint16_t volatile *)DMA1_9_X_COUNT)
#define bfin_read_DMA1_9_X_COUNT()   bfin_read16(DMA1_9_X_COUNT)
#define bfin_write_DMA1_9_X_COUNT(val)   bfin_write16(DMA1_9_X_COUNT, val)
#define pDMA1_9_Y_COUNT   ((uint16_t volatile *)DMA1_9_Y_COUNT)
#define bfin_read_DMA1_9_Y_COUNT()   bfin_read16(DMA1_9_Y_COUNT)
#define bfin_write_DMA1_9_Y_COUNT(val)   bfin_write16(DMA1_9_Y_COUNT, val)
#define pDMA1_9_X_MODIFY   ((uint16_t volatile *)DMA1_9_X_MODIFY)
#define bfin_read_DMA1_9_X_MODIFY()   bfin_read16(DMA1_9_X_MODIFY)
#define bfin_write_DMA1_9_X_MODIFY(val)   bfin_write16(DMA1_9_X_MODIFY, val)
#define pDMA1_9_Y_MODIFY   ((uint16_t volatile *)DMA1_9_Y_MODIFY)
#define bfin_read_DMA1_9_Y_MODIFY()   bfin_read16(DMA1_9_Y_MODIFY)
#define bfin_write_DMA1_9_Y_MODIFY(val)   bfin_write16(DMA1_9_Y_MODIFY, val)
#define pDMA1_9_CURR_DESC_PTR   ((void * volatile *)DMA1_9_CURR_DESC_PTR)
#define bfin_read_DMA1_9_CURR_DESC_PTR()   bfin_readPTR(DMA1_9_CURR_DESC_PTR)
#define bfin_write_DMA1_9_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
#define pDMA1_9_CURR_ADDR   ((void * volatile *)DMA1_9_CURR_ADDR)
#define bfin_read_DMA1_9_CURR_ADDR()   bfin_readPTR(DMA1_9_CURR_ADDR)
#define bfin_write_DMA1_9_CURR_ADDR(val)   bfin_writePTR(DMA1_9_CURR_ADDR, val)
#define pDMA1_9_CURR_X_COUNT   ((uint16_t volatile *)DMA1_9_CURR_X_COUNT)
#define bfin_read_DMA1_9_CURR_X_COUNT()   bfin_read16(DMA1_9_CURR_X_COUNT)
#define bfin_write_DMA1_9_CURR_X_COUNT(val)   bfin_write16(DMA1_9_CURR_X_COUNT, val)
#define pDMA1_9_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT)
#define bfin_read_DMA1_9_CURR_Y_COUNT()   bfin_read16(DMA1_9_CURR_Y_COUNT)
#define bfin_write_DMA1_9_CURR_Y_COUNT(val)   bfin_write16(DMA1_9_CURR_Y_COUNT, val)
#define pDMA1_9_IRQ_STATUS   ((uint16_t volatile *)DMA1_9_IRQ_STATUS)
#define bfin_read_DMA1_9_IRQ_STATUS()   bfin_read16(DMA1_9_IRQ_STATUS)
#define bfin_write_DMA1_9_IRQ_STATUS(val)   bfin_write16(DMA1_9_IRQ_STATUS, val)
#define pDMA1_9_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP)
#define bfin_read_DMA1_9_PERIPHERAL_MAP()   bfin_read16(DMA1_9_PERIPHERAL_MAP)
#define bfin_write_DMA1_9_PERIPHERAL_MAP(val)   bfin_write16(DMA1_9_PERIPHERAL_MAP, val)
#define pDMA1_10_CONFIG   ((uint16_t volatile *)DMA1_10_CONFIG)
#define bfin_read_DMA1_10_CONFIG()   bfin_read16(DMA1_10_CONFIG)
#define bfin_write_DMA1_10_CONFIG(val)   bfin_write16(DMA1_10_CONFIG, val)
#define pDMA1_10_NEXT_DESC_PTR   ((void * volatile *)DMA1_10_NEXT_DESC_PTR)
#define bfin_read_DMA1_10_NEXT_DESC_PTR()   bfin_readPTR(DMA1_10_NEXT_DESC_PTR)
#define bfin_write_DMA1_10_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
#define pDMA1_10_START_ADDR   ((void * volatile *)DMA1_10_START_ADDR)
#define bfin_read_DMA1_10_START_ADDR()   bfin_readPTR(DMA1_10_START_ADDR)
#define bfin_write_DMA1_10_START_ADDR(val)   bfin_writePTR(DMA1_10_START_ADDR, val)
#define pDMA1_10_X_COUNT   ((uint16_t volatile *)DMA1_10_X_COUNT)
#define bfin_read_DMA1_10_X_COUNT()   bfin_read16(DMA1_10_X_COUNT)
#define bfin_write_DMA1_10_X_COUNT(val)   bfin_write16(DMA1_10_X_COUNT, val)
#define pDMA1_10_Y_COUNT   ((uint16_t volatile *)DMA1_10_Y_COUNT)
#define bfin_read_DMA1_10_Y_COUNT()   bfin_read16(DMA1_10_Y_COUNT)
#define bfin_write_DMA1_10_Y_COUNT(val)   bfin_write16(DMA1_10_Y_COUNT, val)
#define pDMA1_10_X_MODIFY   ((uint16_t volatile *)DMA1_10_X_MODIFY)
#define bfin_read_DMA1_10_X_MODIFY()   bfin_read16(DMA1_10_X_MODIFY)
#define bfin_write_DMA1_10_X_MODIFY(val)   bfin_write16(DMA1_10_X_MODIFY, val)
#define pDMA1_10_Y_MODIFY   ((uint16_t volatile *)DMA1_10_Y_MODIFY)
#define bfin_read_DMA1_10_Y_MODIFY()   bfin_read16(DMA1_10_Y_MODIFY)
#define bfin_write_DMA1_10_Y_MODIFY(val)   bfin_write16(DMA1_10_Y_MODIFY, val)
#define pDMA1_10_CURR_DESC_PTR   ((void * volatile *)DMA1_10_CURR_DESC_PTR)
#define bfin_read_DMA1_10_CURR_DESC_PTR()   bfin_readPTR(DMA1_10_CURR_DESC_PTR)
#define bfin_write_DMA1_10_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
#define pDMA1_10_CURR_ADDR   ((void * volatile *)DMA1_10_CURR_ADDR)
#define bfin_read_DMA1_10_CURR_ADDR()   bfin_readPTR(DMA1_10_CURR_ADDR)
#define bfin_write_DMA1_10_CURR_ADDR(val)   bfin_writePTR(DMA1_10_CURR_ADDR, val)
#define pDMA1_10_CURR_X_COUNT   ((uint16_t volatile *)DMA1_10_CURR_X_COUNT)
#define bfin_read_DMA1_10_CURR_X_COUNT()   bfin_read16(DMA1_10_CURR_X_COUNT)
#define bfin_write_DMA1_10_CURR_X_COUNT(val)   bfin_write16(DMA1_10_CURR_X_COUNT, val)
#define pDMA1_10_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT)
#define bfin_read_DMA1_10_CURR_Y_COUNT()   bfin_read16(DMA1_10_CURR_Y_COUNT)
#define bfin_write_DMA1_10_CURR_Y_COUNT(val)   bfin_write16(DMA1_10_CURR_Y_COUNT, val)
#define pDMA1_10_IRQ_STATUS   ((uint16_t volatile *)DMA1_10_IRQ_STATUS)
#define bfin_read_DMA1_10_IRQ_STATUS()   bfin_read16(DMA1_10_IRQ_STATUS)
#define bfin_write_DMA1_10_IRQ_STATUS(val)   bfin_write16(DMA1_10_IRQ_STATUS, val)
#define pDMA1_10_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP)
#define bfin_read_DMA1_10_PERIPHERAL_MAP()   bfin_read16(DMA1_10_PERIPHERAL_MAP)
#define bfin_write_DMA1_10_PERIPHERAL_MAP(val)   bfin_write16(DMA1_10_PERIPHERAL_MAP, val)
#define pDMA1_11_CONFIG   ((uint16_t volatile *)DMA1_11_CONFIG)
#define bfin_read_DMA1_11_CONFIG()   bfin_read16(DMA1_11_CONFIG)
#define bfin_write_DMA1_11_CONFIG(val)   bfin_write16(DMA1_11_CONFIG, val)
#define pDMA1_11_NEXT_DESC_PTR   ((void * volatile *)DMA1_11_NEXT_DESC_PTR)
#define bfin_read_DMA1_11_NEXT_DESC_PTR()   bfin_readPTR(DMA1_11_NEXT_DESC_PTR)
#define bfin_write_DMA1_11_NEXT_DESC_PTR(val)   bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
#define pDMA1_11_START_ADDR   ((void * volatile *)DMA1_11_START_ADDR)
#define bfin_read_DMA1_11_START_ADDR()   bfin_readPTR(DMA1_11_START_ADDR)
#define bfin_write_DMA1_11_START_ADDR(val)   bfin_writePTR(DMA1_11_START_ADDR, val)
#define pDMA1_11_X_COUNT   ((uint16_t volatile *)DMA1_11_X_COUNT)
#define bfin_read_DMA1_11_X_COUNT()   bfin_read16(DMA1_11_X_COUNT)
#define bfin_write_DMA1_11_X_COUNT(val)   bfin_write16(DMA1_11_X_COUNT, val)
#define pDMA1_11_Y_COUNT   ((uint16_t volatile *)DMA1_11_Y_COUNT)
#define bfin_read_DMA1_11_Y_COUNT()   bfin_read16(DMA1_11_Y_COUNT)
#define bfin_write_DMA1_11_Y_COUNT(val)   bfin_write16(DMA1_11_Y_COUNT, val)
#define pDMA1_11_X_MODIFY   ((uint16_t volatile *)DMA1_11_X_MODIFY)
#define bfin_read_DMA1_11_X_MODIFY()   bfin_read16(DMA1_11_X_MODIFY)
#define bfin_write_DMA1_11_X_MODIFY(val)   bfin_write16(DMA1_11_X_MODIFY, val)
#define pDMA1_11_Y_MODIFY   ((uint16_t volatile *)DMA1_11_Y_MODIFY)
#define bfin_read_DMA1_11_Y_MODIFY()   bfin_read16(DMA1_11_Y_MODIFY)
#define bfin_write_DMA1_11_Y_MODIFY(val)   bfin_write16(DMA1_11_Y_MODIFY, val)
#define pDMA1_11_CURR_DESC_PTR   ((void * volatile *)DMA1_11_CURR_DESC_PTR)
#define bfin_read_DMA1_11_CURR_DESC_PTR()   bfin_readPTR(DMA1_11_CURR_DESC_PTR)
#define bfin_write_DMA1_11_CURR_DESC_PTR(val)   bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
#define pDMA1_11_CURR_ADDR   ((void * volatile *)DMA1_11_CURR_ADDR)
#define bfin_read_DMA1_11_CURR_ADDR()   bfin_readPTR(DMA1_11_CURR_ADDR)
#define bfin_write_DMA1_11_CURR_ADDR(val)   bfin_writePTR(DMA1_11_CURR_ADDR, val)
#define pDMA1_11_CURR_X_COUNT   ((uint16_t volatile *)DMA1_11_CURR_X_COUNT)
#define bfin_read_DMA1_11_CURR_X_COUNT()   bfin_read16(DMA1_11_CURR_X_COUNT)
#define bfin_write_DMA1_11_CURR_X_COUNT(val)   bfin_write16(DMA1_11_CURR_X_COUNT, val)
#define pDMA1_11_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT)
#define bfin_read_DMA1_11_CURR_Y_COUNT()   bfin_read16(DMA1_11_CURR_Y_COUNT)
#define bfin_write_DMA1_11_CURR_Y_COUNT(val)   bfin_write16(DMA1_11_CURR_Y_COUNT, val)
#define pDMA1_11_IRQ_STATUS   ((uint16_t volatile *)DMA1_11_IRQ_STATUS)
#define bfin_read_DMA1_11_IRQ_STATUS()   bfin_read16(DMA1_11_IRQ_STATUS)
#define bfin_write_DMA1_11_IRQ_STATUS(val)   bfin_write16(DMA1_11_IRQ_STATUS, val)
#define pDMA1_11_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP)
#define bfin_read_DMA1_11_PERIPHERAL_MAP()   bfin_read16(DMA1_11_PERIPHERAL_MAP)
#define bfin_write_DMA1_11_PERIPHERAL_MAP(val)   bfin_write16(DMA1_11_PERIPHERAL_MAP, val)
#define pDMA2_TC_PER   ((uint16_t volatile *)DMA2_TC_PER)
#define bfin_read_DMA2_TC_PER()   bfin_read16(DMA2_TC_PER)
#define bfin_write_DMA2_TC_PER(val)   bfin_write16(DMA2_TC_PER, val)
#define pDMA2_TC_CNT   ((uint16_t volatile *)DMA2_TC_CNT)
#define bfin_read_DMA2_TC_CNT()   bfin_read16(DMA2_TC_CNT)
#define bfin_write_DMA2_TC_CNT(val)   bfin_write16(DMA2_TC_CNT, val)
#define pDMA2_0_CONFIG   ((uint16_t volatile *)DMA2_0_CONFIG)
#define bfin_read_DMA2_0_CONFIG()   bfin_read16(DMA2_0_CONFIG)
#define bfin_write_DMA2_0_CONFIG(val)   bfin_write16(DMA2_0_CONFIG, val)
#define pDMA2_0_NEXT_DESC_PTR   ((void * volatile *)DMA2_0_NEXT_DESC_PTR)
#define bfin_read_DMA2_0_NEXT_DESC_PTR()   bfin_readPTR(DMA2_0_NEXT_DESC_PTR)
#define bfin_write_DMA2_0_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
#define pDMA2_0_START_ADDR   ((void * volatile *)DMA2_0_START_ADDR)
#define bfin_read_DMA2_0_START_ADDR()   bfin_readPTR(DMA2_0_START_ADDR)
#define bfin_write_DMA2_0_START_ADDR(val)   bfin_writePTR(DMA2_0_START_ADDR, val)
#define pDMA2_0_X_COUNT   ((uint16_t volatile *)DMA2_0_X_COUNT)
#define bfin_read_DMA2_0_X_COUNT()   bfin_read16(DMA2_0_X_COUNT)
#define bfin_write_DMA2_0_X_COUNT(val)   bfin_write16(DMA2_0_X_COUNT, val)
#define pDMA2_0_Y_COUNT   ((uint16_t volatile *)DMA2_0_Y_COUNT)
#define bfin_read_DMA2_0_Y_COUNT()   bfin_read16(DMA2_0_Y_COUNT)
#define bfin_write_DMA2_0_Y_COUNT(val)   bfin_write16(DMA2_0_Y_COUNT, val)
#define pDMA2_0_X_MODIFY   ((uint16_t volatile *)DMA2_0_X_MODIFY)
#define bfin_read_DMA2_0_X_MODIFY()   bfin_read16(DMA2_0_X_MODIFY)
#define bfin_write_DMA2_0_X_MODIFY(val)   bfin_write16(DMA2_0_X_MODIFY, val)
#define pDMA2_0_Y_MODIFY   ((uint16_t volatile *)DMA2_0_Y_MODIFY)
#define bfin_read_DMA2_0_Y_MODIFY()   bfin_read16(DMA2_0_Y_MODIFY)
#define bfin_write_DMA2_0_Y_MODIFY(val)   bfin_write16(DMA2_0_Y_MODIFY, val)
#define pDMA2_0_CURR_DESC_PTR   ((void * volatile *)DMA2_0_CURR_DESC_PTR)
#define bfin_read_DMA2_0_CURR_DESC_PTR()   bfin_readPTR(DMA2_0_CURR_DESC_PTR)
#define bfin_write_DMA2_0_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
#define pDMA2_0_CURR_ADDR   ((void * volatile *)DMA2_0_CURR_ADDR)
#define bfin_read_DMA2_0_CURR_ADDR()   bfin_readPTR(DMA2_0_CURR_ADDR)
#define bfin_write_DMA2_0_CURR_ADDR(val)   bfin_writePTR(DMA2_0_CURR_ADDR, val)
#define pDMA2_0_CURR_X_COUNT   ((uint16_t volatile *)DMA2_0_CURR_X_COUNT)
#define bfin_read_DMA2_0_CURR_X_COUNT()   bfin_read16(DMA2_0_CURR_X_COUNT)
#define bfin_write_DMA2_0_CURR_X_COUNT(val)   bfin_write16(DMA2_0_CURR_X_COUNT, val)
#define pDMA2_0_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT)
#define bfin_read_DMA2_0_CURR_Y_COUNT()   bfin_read16(DMA2_0_CURR_Y_COUNT)
#define bfin_write_DMA2_0_CURR_Y_COUNT(val)   bfin_write16(DMA2_0_CURR_Y_COUNT, val)
#define pDMA2_0_IRQ_STATUS   ((uint16_t volatile *)DMA2_0_IRQ_STATUS)
#define bfin_read_DMA2_0_IRQ_STATUS()   bfin_read16(DMA2_0_IRQ_STATUS)
#define bfin_write_DMA2_0_IRQ_STATUS(val)   bfin_write16(DMA2_0_IRQ_STATUS, val)
#define pDMA2_0_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP)
#define bfin_read_DMA2_0_PERIPHERAL_MAP()   bfin_read16(DMA2_0_PERIPHERAL_MAP)
#define bfin_write_DMA2_0_PERIPHERAL_MAP(val)   bfin_write16(DMA2_0_PERIPHERAL_MAP, val)
#define pDMA2_1_CONFIG   ((uint16_t volatile *)DMA2_1_CONFIG)
#define bfin_read_DMA2_1_CONFIG()   bfin_read16(DMA2_1_CONFIG)
#define bfin_write_DMA2_1_CONFIG(val)   bfin_write16(DMA2_1_CONFIG, val)
#define pDMA2_1_NEXT_DESC_PTR   ((void * volatile *)DMA2_1_NEXT_DESC_PTR)
#define bfin_read_DMA2_1_NEXT_DESC_PTR()   bfin_readPTR(DMA2_1_NEXT_DESC_PTR)
#define bfin_write_DMA2_1_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
#define pDMA2_1_START_ADDR   ((void * volatile *)DMA2_1_START_ADDR)
#define bfin_read_DMA2_1_START_ADDR()   bfin_readPTR(DMA2_1_START_ADDR)
#define bfin_write_DMA2_1_START_ADDR(val)   bfin_writePTR(DMA2_1_START_ADDR, val)
#define pDMA2_1_X_COUNT   ((uint16_t volatile *)DMA2_1_X_COUNT)
#define bfin_read_DMA2_1_X_COUNT()   bfin_read16(DMA2_1_X_COUNT)
#define bfin_write_DMA2_1_X_COUNT(val)   bfin_write16(DMA2_1_X_COUNT, val)
#define pDMA2_1_Y_COUNT   ((uint16_t volatile *)DMA2_1_Y_COUNT)
#define bfin_read_DMA2_1_Y_COUNT()   bfin_read16(DMA2_1_Y_COUNT)
#define bfin_write_DMA2_1_Y_COUNT(val)   bfin_write16(DMA2_1_Y_COUNT, val)
#define pDMA2_1_X_MODIFY   ((uint16_t volatile *)DMA2_1_X_MODIFY)
#define bfin_read_DMA2_1_X_MODIFY()   bfin_read16(DMA2_1_X_MODIFY)
#define bfin_write_DMA2_1_X_MODIFY(val)   bfin_write16(DMA2_1_X_MODIFY, val)
#define pDMA2_1_Y_MODIFY   ((uint16_t volatile *)DMA2_1_Y_MODIFY)
#define bfin_read_DMA2_1_Y_MODIFY()   bfin_read16(DMA2_1_Y_MODIFY)
#define bfin_write_DMA2_1_Y_MODIFY(val)   bfin_write16(DMA2_1_Y_MODIFY, val)
#define pDMA2_1_CURR_DESC_PTR   ((void * volatile *)DMA2_1_CURR_DESC_PTR)
#define bfin_read_DMA2_1_CURR_DESC_PTR()   bfin_readPTR(DMA2_1_CURR_DESC_PTR)
#define bfin_write_DMA2_1_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
#define pDMA2_1_CURR_ADDR   ((void * volatile *)DMA2_1_CURR_ADDR)
#define bfin_read_DMA2_1_CURR_ADDR()   bfin_readPTR(DMA2_1_CURR_ADDR)
#define bfin_write_DMA2_1_CURR_ADDR(val)   bfin_writePTR(DMA2_1_CURR_ADDR, val)
#define pDMA2_1_CURR_X_COUNT   ((uint16_t volatile *)DMA2_1_CURR_X_COUNT)
#define bfin_read_DMA2_1_CURR_X_COUNT()   bfin_read16(DMA2_1_CURR_X_COUNT)
#define bfin_write_DMA2_1_CURR_X_COUNT(val)   bfin_write16(DMA2_1_CURR_X_COUNT, val)
#define pDMA2_1_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT)
#define bfin_read_DMA2_1_CURR_Y_COUNT()   bfin_read16(DMA2_1_CURR_Y_COUNT)
#define bfin_write_DMA2_1_CURR_Y_COUNT(val)   bfin_write16(DMA2_1_CURR_Y_COUNT, val)
#define pDMA2_1_IRQ_STATUS   ((uint16_t volatile *)DMA2_1_IRQ_STATUS)
#define bfin_read_DMA2_1_IRQ_STATUS()   bfin_read16(DMA2_1_IRQ_STATUS)
#define bfin_write_DMA2_1_IRQ_STATUS(val)   bfin_write16(DMA2_1_IRQ_STATUS, val)
#define pDMA2_1_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP)
#define bfin_read_DMA2_1_PERIPHERAL_MAP()   bfin_read16(DMA2_1_PERIPHERAL_MAP)
#define bfin_write_DMA2_1_PERIPHERAL_MAP(val)   bfin_write16(DMA2_1_PERIPHERAL_MAP, val)
#define pDMA2_2_CONFIG   ((uint16_t volatile *)DMA2_2_CONFIG)
#define bfin_read_DMA2_2_CONFIG()   bfin_read16(DMA2_2_CONFIG)
#define bfin_write_DMA2_2_CONFIG(val)   bfin_write16(DMA2_2_CONFIG, val)
#define pDMA2_2_NEXT_DESC_PTR   ((void * volatile *)DMA2_2_NEXT_DESC_PTR)
#define bfin_read_DMA2_2_NEXT_DESC_PTR()   bfin_readPTR(DMA2_2_NEXT_DESC_PTR)
#define bfin_write_DMA2_2_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
#define pDMA2_2_START_ADDR   ((void * volatile *)DMA2_2_START_ADDR)
#define bfin_read_DMA2_2_START_ADDR()   bfin_readPTR(DMA2_2_START_ADDR)
#define bfin_write_DMA2_2_START_ADDR(val)   bfin_writePTR(DMA2_2_START_ADDR, val)
#define pDMA2_2_X_COUNT   ((uint16_t volatile *)DMA2_2_X_COUNT)
#define bfin_read_DMA2_2_X_COUNT()   bfin_read16(DMA2_2_X_COUNT)
#define bfin_write_DMA2_2_X_COUNT(val)   bfin_write16(DMA2_2_X_COUNT, val)
#define pDMA2_2_Y_COUNT   ((uint16_t volatile *)DMA2_2_Y_COUNT)
#define bfin_read_DMA2_2_Y_COUNT()   bfin_read16(DMA2_2_Y_COUNT)
#define bfin_write_DMA2_2_Y_COUNT(val)   bfin_write16(DMA2_2_Y_COUNT, val)
#define pDMA2_2_X_MODIFY   ((uint16_t volatile *)DMA2_2_X_MODIFY)
#define bfin_read_DMA2_2_X_MODIFY()   bfin_read16(DMA2_2_X_MODIFY)
#define bfin_write_DMA2_2_X_MODIFY(val)   bfin_write16(DMA2_2_X_MODIFY, val)
#define pDMA2_2_Y_MODIFY   ((uint16_t volatile *)DMA2_2_Y_MODIFY)
#define bfin_read_DMA2_2_Y_MODIFY()   bfin_read16(DMA2_2_Y_MODIFY)
#define bfin_write_DMA2_2_Y_MODIFY(val)   bfin_write16(DMA2_2_Y_MODIFY, val)
#define pDMA2_2_CURR_DESC_PTR   ((void * volatile *)DMA2_2_CURR_DESC_PTR)
#define bfin_read_DMA2_2_CURR_DESC_PTR()   bfin_readPTR(DMA2_2_CURR_DESC_PTR)
#define bfin_write_DMA2_2_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
#define pDMA2_2_CURR_ADDR   ((void * volatile *)DMA2_2_CURR_ADDR)
#define bfin_read_DMA2_2_CURR_ADDR()   bfin_readPTR(DMA2_2_CURR_ADDR)
#define bfin_write_DMA2_2_CURR_ADDR(val)   bfin_writePTR(DMA2_2_CURR_ADDR, val)
#define pDMA2_2_CURR_X_COUNT   ((uint16_t volatile *)DMA2_2_CURR_X_COUNT)
#define bfin_read_DMA2_2_CURR_X_COUNT()   bfin_read16(DMA2_2_CURR_X_COUNT)
#define bfin_write_DMA2_2_CURR_X_COUNT(val)   bfin_write16(DMA2_2_CURR_X_COUNT, val)
#define pDMA2_2_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT)
#define bfin_read_DMA2_2_CURR_Y_COUNT()   bfin_read16(DMA2_2_CURR_Y_COUNT)
#define bfin_write_DMA2_2_CURR_Y_COUNT(val)   bfin_write16(DMA2_2_CURR_Y_COUNT, val)
#define pDMA2_2_IRQ_STATUS   ((uint16_t volatile *)DMA2_2_IRQ_STATUS)
#define bfin_read_DMA2_2_IRQ_STATUS()   bfin_read16(DMA2_2_IRQ_STATUS)
#define bfin_write_DMA2_2_IRQ_STATUS(val)   bfin_write16(DMA2_2_IRQ_STATUS, val)
#define pDMA2_2_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP)
#define bfin_read_DMA2_2_PERIPHERAL_MAP()   bfin_read16(DMA2_2_PERIPHERAL_MAP)
#define bfin_write_DMA2_2_PERIPHERAL_MAP(val)   bfin_write16(DMA2_2_PERIPHERAL_MAP, val)
#define pDMA2_3_CONFIG   ((uint16_t volatile *)DMA2_3_CONFIG)
#define bfin_read_DMA2_3_CONFIG()   bfin_read16(DMA2_3_CONFIG)
#define bfin_write_DMA2_3_CONFIG(val)   bfin_write16(DMA2_3_CONFIG, val)
#define pDMA2_3_NEXT_DESC_PTR   ((void * volatile *)DMA2_3_NEXT_DESC_PTR)
#define bfin_read_DMA2_3_NEXT_DESC_PTR()   bfin_readPTR(DMA2_3_NEXT_DESC_PTR)
#define bfin_write_DMA2_3_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
#define pDMA2_3_START_ADDR   ((void * volatile *)DMA2_3_START_ADDR)
#define bfin_read_DMA2_3_START_ADDR()   bfin_readPTR(DMA2_3_START_ADDR)
#define bfin_write_DMA2_3_START_ADDR(val)   bfin_writePTR(DMA2_3_START_ADDR, val)
#define pDMA2_3_X_COUNT   ((uint16_t volatile *)DMA2_3_X_COUNT)
#define bfin_read_DMA2_3_X_COUNT()   bfin_read16(DMA2_3_X_COUNT)
#define bfin_write_DMA2_3_X_COUNT(val)   bfin_write16(DMA2_3_X_COUNT, val)
#define pDMA2_3_Y_COUNT   ((uint16_t volatile *)DMA2_3_Y_COUNT)
#define bfin_read_DMA2_3_Y_COUNT()   bfin_read16(DMA2_3_Y_COUNT)
#define bfin_write_DMA2_3_Y_COUNT(val)   bfin_write16(DMA2_3_Y_COUNT, val)
#define pDMA2_3_X_MODIFY   ((uint16_t volatile *)DMA2_3_X_MODIFY)
#define bfin_read_DMA2_3_X_MODIFY()   bfin_read16(DMA2_3_X_MODIFY)
#define bfin_write_DMA2_3_X_MODIFY(val)   bfin_write16(DMA2_3_X_MODIFY, val)
#define pDMA2_3_Y_MODIFY   ((uint16_t volatile *)DMA2_3_Y_MODIFY)
#define bfin_read_DMA2_3_Y_MODIFY()   bfin_read16(DMA2_3_Y_MODIFY)
#define bfin_write_DMA2_3_Y_MODIFY(val)   bfin_write16(DMA2_3_Y_MODIFY, val)
#define pDMA2_3_CURR_DESC_PTR   ((void * volatile *)DMA2_3_CURR_DESC_PTR)
#define bfin_read_DMA2_3_CURR_DESC_PTR()   bfin_readPTR(DMA2_3_CURR_DESC_PTR)
#define bfin_write_DMA2_3_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
#define pDMA2_3_CURR_ADDR   ((void * volatile *)DMA2_3_CURR_ADDR)
#define bfin_read_DMA2_3_CURR_ADDR()   bfin_readPTR(DMA2_3_CURR_ADDR)
#define bfin_write_DMA2_3_CURR_ADDR(val)   bfin_writePTR(DMA2_3_CURR_ADDR, val)
#define pDMA2_3_CURR_X_COUNT   ((uint16_t volatile *)DMA2_3_CURR_X_COUNT)
#define bfin_read_DMA2_3_CURR_X_COUNT()   bfin_read16(DMA2_3_CURR_X_COUNT)
#define bfin_write_DMA2_3_CURR_X_COUNT(val)   bfin_write16(DMA2_3_CURR_X_COUNT, val)
#define pDMA2_3_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT)
#define bfin_read_DMA2_3_CURR_Y_COUNT()   bfin_read16(DMA2_3_CURR_Y_COUNT)
#define bfin_write_DMA2_3_CURR_Y_COUNT(val)   bfin_write16(DMA2_3_CURR_Y_COUNT, val)
#define pDMA2_3_IRQ_STATUS   ((uint16_t volatile *)DMA2_3_IRQ_STATUS)
#define bfin_read_DMA2_3_IRQ_STATUS()   bfin_read16(DMA2_3_IRQ_STATUS)
#define bfin_write_DMA2_3_IRQ_STATUS(val)   bfin_write16(DMA2_3_IRQ_STATUS, val)
#define pDMA2_3_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP)
#define bfin_read_DMA2_3_PERIPHERAL_MAP()   bfin_read16(DMA2_3_PERIPHERAL_MAP)
#define bfin_write_DMA2_3_PERIPHERAL_MAP(val)   bfin_write16(DMA2_3_PERIPHERAL_MAP, val)
#define pDMA2_4_CONFIG   ((uint16_t volatile *)DMA2_4_CONFIG)
#define bfin_read_DMA2_4_CONFIG()   bfin_read16(DMA2_4_CONFIG)
#define bfin_write_DMA2_4_CONFIG(val)   bfin_write16(DMA2_4_CONFIG, val)
#define pDMA2_4_NEXT_DESC_PTR   ((void * volatile *)DMA2_4_NEXT_DESC_PTR)
#define bfin_read_DMA2_4_NEXT_DESC_PTR()   bfin_readPTR(DMA2_4_NEXT_DESC_PTR)
#define bfin_write_DMA2_4_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
#define pDMA2_4_START_ADDR   ((void * volatile *)DMA2_4_START_ADDR)
#define bfin_read_DMA2_4_START_ADDR()   bfin_readPTR(DMA2_4_START_ADDR)
#define bfin_write_DMA2_4_START_ADDR(val)   bfin_writePTR(DMA2_4_START_ADDR, val)
#define pDMA2_4_X_COUNT   ((uint16_t volatile *)DMA2_4_X_COUNT)
#define bfin_read_DMA2_4_X_COUNT()   bfin_read16(DMA2_4_X_COUNT)
#define bfin_write_DMA2_4_X_COUNT(val)   bfin_write16(DMA2_4_X_COUNT, val)
#define pDMA2_4_Y_COUNT   ((uint16_t volatile *)DMA2_4_Y_COUNT)
#define bfin_read_DMA2_4_Y_COUNT()   bfin_read16(DMA2_4_Y_COUNT)
#define bfin_write_DMA2_4_Y_COUNT(val)   bfin_write16(DMA2_4_Y_COUNT, val)
#define pDMA2_4_X_MODIFY   ((uint16_t volatile *)DMA2_4_X_MODIFY)
#define bfin_read_DMA2_4_X_MODIFY()   bfin_read16(DMA2_4_X_MODIFY)
#define bfin_write_DMA2_4_X_MODIFY(val)   bfin_write16(DMA2_4_X_MODIFY, val)
#define pDMA2_4_Y_MODIFY   ((uint16_t volatile *)DMA2_4_Y_MODIFY)
#define bfin_read_DMA2_4_Y_MODIFY()   bfin_read16(DMA2_4_Y_MODIFY)
#define bfin_write_DMA2_4_Y_MODIFY(val)   bfin_write16(DMA2_4_Y_MODIFY, val)
#define pDMA2_4_CURR_DESC_PTR   ((void * volatile *)DMA2_4_CURR_DESC_PTR)
#define bfin_read_DMA2_4_CURR_DESC_PTR()   bfin_readPTR(DMA2_4_CURR_DESC_PTR)
#define bfin_write_DMA2_4_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
#define pDMA2_4_CURR_ADDR   ((void * volatile *)DMA2_4_CURR_ADDR)
#define bfin_read_DMA2_4_CURR_ADDR()   bfin_readPTR(DMA2_4_CURR_ADDR)
#define bfin_write_DMA2_4_CURR_ADDR(val)   bfin_writePTR(DMA2_4_CURR_ADDR, val)
#define pDMA2_4_CURR_X_COUNT   ((uint16_t volatile *)DMA2_4_CURR_X_COUNT)
#define bfin_read_DMA2_4_CURR_X_COUNT()   bfin_read16(DMA2_4_CURR_X_COUNT)
#define bfin_write_DMA2_4_CURR_X_COUNT(val)   bfin_write16(DMA2_4_CURR_X_COUNT, val)
#define pDMA2_4_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT)
#define bfin_read_DMA2_4_CURR_Y_COUNT()   bfin_read16(DMA2_4_CURR_Y_COUNT)
#define bfin_write_DMA2_4_CURR_Y_COUNT(val)   bfin_write16(DMA2_4_CURR_Y_COUNT, val)
#define pDMA2_4_IRQ_STATUS   ((uint16_t volatile *)DMA2_4_IRQ_STATUS)
#define bfin_read_DMA2_4_IRQ_STATUS()   bfin_read16(DMA2_4_IRQ_STATUS)
#define bfin_write_DMA2_4_IRQ_STATUS(val)   bfin_write16(DMA2_4_IRQ_STATUS, val)
#define pDMA2_4_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP)
#define bfin_read_DMA2_4_PERIPHERAL_MAP()   bfin_read16(DMA2_4_PERIPHERAL_MAP)
#define bfin_write_DMA2_4_PERIPHERAL_MAP(val)   bfin_write16(DMA2_4_PERIPHERAL_MAP, val)
#define pDMA2_5_CONFIG   ((uint16_t volatile *)DMA2_5_CONFIG)
#define bfin_read_DMA2_5_CONFIG()   bfin_read16(DMA2_5_CONFIG)
#define bfin_write_DMA2_5_CONFIG(val)   bfin_write16(DMA2_5_CONFIG, val)
#define pDMA2_5_NEXT_DESC_PTR   ((void * volatile *)DMA2_5_NEXT_DESC_PTR)
#define bfin_read_DMA2_5_NEXT_DESC_PTR()   bfin_readPTR(DMA2_5_NEXT_DESC_PTR)
#define bfin_write_DMA2_5_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
#define pDMA2_5_START_ADDR   ((void * volatile *)DMA2_5_START_ADDR)
#define bfin_read_DMA2_5_START_ADDR()   bfin_readPTR(DMA2_5_START_ADDR)
#define bfin_write_DMA2_5_START_ADDR(val)   bfin_writePTR(DMA2_5_START_ADDR, val)
#define pDMA2_5_X_COUNT   ((uint16_t volatile *)DMA2_5_X_COUNT)
#define bfin_read_DMA2_5_X_COUNT()   bfin_read16(DMA2_5_X_COUNT)
#define bfin_write_DMA2_5_X_COUNT(val)   bfin_write16(DMA2_5_X_COUNT, val)
#define pDMA2_5_Y_COUNT   ((uint16_t volatile *)DMA2_5_Y_COUNT)
#define bfin_read_DMA2_5_Y_COUNT()   bfin_read16(DMA2_5_Y_COUNT)
#define bfin_write_DMA2_5_Y_COUNT(val)   bfin_write16(DMA2_5_Y_COUNT, val)
#define pDMA2_5_X_MODIFY   ((uint16_t volatile *)DMA2_5_X_MODIFY)
#define bfin_read_DMA2_5_X_MODIFY()   bfin_read16(DMA2_5_X_MODIFY)
#define bfin_write_DMA2_5_X_MODIFY(val)   bfin_write16(DMA2_5_X_MODIFY, val)
#define pDMA2_5_Y_MODIFY   ((uint16_t volatile *)DMA2_5_Y_MODIFY)
#define bfin_read_DMA2_5_Y_MODIFY()   bfin_read16(DMA2_5_Y_MODIFY)
#define bfin_write_DMA2_5_Y_MODIFY(val)   bfin_write16(DMA2_5_Y_MODIFY, val)
#define pDMA2_5_CURR_DESC_PTR   ((void * volatile *)DMA2_5_CURR_DESC_PTR)
#define bfin_read_DMA2_5_CURR_DESC_PTR()   bfin_readPTR(DMA2_5_CURR_DESC_PTR)
#define bfin_write_DMA2_5_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
#define pDMA2_5_CURR_ADDR   ((void * volatile *)DMA2_5_CURR_ADDR)
#define bfin_read_DMA2_5_CURR_ADDR()   bfin_readPTR(DMA2_5_CURR_ADDR)
#define bfin_write_DMA2_5_CURR_ADDR(val)   bfin_writePTR(DMA2_5_CURR_ADDR, val)
#define pDMA2_5_CURR_X_COUNT   ((uint16_t volatile *)DMA2_5_CURR_X_COUNT)
#define bfin_read_DMA2_5_CURR_X_COUNT()   bfin_read16(DMA2_5_CURR_X_COUNT)
#define bfin_write_DMA2_5_CURR_X_COUNT(val)   bfin_write16(DMA2_5_CURR_X_COUNT, val)
#define pDMA2_5_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT)
#define bfin_read_DMA2_5_CURR_Y_COUNT()   bfin_read16(DMA2_5_CURR_Y_COUNT)
#define bfin_write_DMA2_5_CURR_Y_COUNT(val)   bfin_write16(DMA2_5_CURR_Y_COUNT, val)
#define pDMA2_5_IRQ_STATUS   ((uint16_t volatile *)DMA2_5_IRQ_STATUS)
#define bfin_read_DMA2_5_IRQ_STATUS()   bfin_read16(DMA2_5_IRQ_STATUS)
#define bfin_write_DMA2_5_IRQ_STATUS(val)   bfin_write16(DMA2_5_IRQ_STATUS, val)
#define pDMA2_5_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP)
#define bfin_read_DMA2_5_PERIPHERAL_MAP()   bfin_read16(DMA2_5_PERIPHERAL_MAP)
#define bfin_write_DMA2_5_PERIPHERAL_MAP(val)   bfin_write16(DMA2_5_PERIPHERAL_MAP, val)
#define pDMA2_6_CONFIG   ((uint16_t volatile *)DMA2_6_CONFIG)
#define bfin_read_DMA2_6_CONFIG()   bfin_read16(DMA2_6_CONFIG)
#define bfin_write_DMA2_6_CONFIG(val)   bfin_write16(DMA2_6_CONFIG, val)
#define pDMA2_6_NEXT_DESC_PTR   ((void * volatile *)DMA2_6_NEXT_DESC_PTR)
#define bfin_read_DMA2_6_NEXT_DESC_PTR()   bfin_readPTR(DMA2_6_NEXT_DESC_PTR)
#define bfin_write_DMA2_6_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
#define pDMA2_6_START_ADDR   ((void * volatile *)DMA2_6_START_ADDR)
#define bfin_read_DMA2_6_START_ADDR()   bfin_readPTR(DMA2_6_START_ADDR)
#define bfin_write_DMA2_6_START_ADDR(val)   bfin_writePTR(DMA2_6_START_ADDR, val)
#define pDMA2_6_X_COUNT   ((uint16_t volatile *)DMA2_6_X_COUNT)
#define bfin_read_DMA2_6_X_COUNT()   bfin_read16(DMA2_6_X_COUNT)
#define bfin_write_DMA2_6_X_COUNT(val)   bfin_write16(DMA2_6_X_COUNT, val)
#define pDMA2_6_Y_COUNT   ((uint16_t volatile *)DMA2_6_Y_COUNT)
#define bfin_read_DMA2_6_Y_COUNT()   bfin_read16(DMA2_6_Y_COUNT)
#define bfin_write_DMA2_6_Y_COUNT(val)   bfin_write16(DMA2_6_Y_COUNT, val)
#define pDMA2_6_X_MODIFY   ((uint16_t volatile *)DMA2_6_X_MODIFY)
#define bfin_read_DMA2_6_X_MODIFY()   bfin_read16(DMA2_6_X_MODIFY)
#define bfin_write_DMA2_6_X_MODIFY(val)   bfin_write16(DMA2_6_X_MODIFY, val)
#define pDMA2_6_Y_MODIFY   ((uint16_t volatile *)DMA2_6_Y_MODIFY)
#define bfin_read_DMA2_6_Y_MODIFY()   bfin_read16(DMA2_6_Y_MODIFY)
#define bfin_write_DMA2_6_Y_MODIFY(val)   bfin_write16(DMA2_6_Y_MODIFY, val)
#define pDMA2_6_CURR_DESC_PTR   ((void * volatile *)DMA2_6_CURR_DESC_PTR)
#define bfin_read_DMA2_6_CURR_DESC_PTR()   bfin_readPTR(DMA2_6_CURR_DESC_PTR)
#define bfin_write_DMA2_6_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
#define pDMA2_6_CURR_ADDR   ((void * volatile *)DMA2_6_CURR_ADDR)
#define bfin_read_DMA2_6_CURR_ADDR()   bfin_readPTR(DMA2_6_CURR_ADDR)
#define bfin_write_DMA2_6_CURR_ADDR(val)   bfin_writePTR(DMA2_6_CURR_ADDR, val)
#define pDMA2_6_CURR_X_COUNT   ((uint16_t volatile *)DMA2_6_CURR_X_COUNT)
#define bfin_read_DMA2_6_CURR_X_COUNT()   bfin_read16(DMA2_6_CURR_X_COUNT)
#define bfin_write_DMA2_6_CURR_X_COUNT(val)   bfin_write16(DMA2_6_CURR_X_COUNT, val)
#define pDMA2_6_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT)
#define bfin_read_DMA2_6_CURR_Y_COUNT()   bfin_read16(DMA2_6_CURR_Y_COUNT)
#define bfin_write_DMA2_6_CURR_Y_COUNT(val)   bfin_write16(DMA2_6_CURR_Y_COUNT, val)
#define pDMA2_6_IRQ_STATUS   ((uint16_t volatile *)DMA2_6_IRQ_STATUS)
#define bfin_read_DMA2_6_IRQ_STATUS()   bfin_read16(DMA2_6_IRQ_STATUS)
#define bfin_write_DMA2_6_IRQ_STATUS(val)   bfin_write16(DMA2_6_IRQ_STATUS, val)
#define pDMA2_6_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP)
#define bfin_read_DMA2_6_PERIPHERAL_MAP()   bfin_read16(DMA2_6_PERIPHERAL_MAP)
#define bfin_write_DMA2_6_PERIPHERAL_MAP(val)   bfin_write16(DMA2_6_PERIPHERAL_MAP, val)
#define pDMA2_7_CONFIG   ((uint16_t volatile *)DMA2_7_CONFIG)
#define bfin_read_DMA2_7_CONFIG()   bfin_read16(DMA2_7_CONFIG)
#define bfin_write_DMA2_7_CONFIG(val)   bfin_write16(DMA2_7_CONFIG, val)
#define pDMA2_7_NEXT_DESC_PTR   ((void * volatile *)DMA2_7_NEXT_DESC_PTR)
#define bfin_read_DMA2_7_NEXT_DESC_PTR()   bfin_readPTR(DMA2_7_NEXT_DESC_PTR)
#define bfin_write_DMA2_7_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
#define pDMA2_7_START_ADDR   ((void * volatile *)DMA2_7_START_ADDR)
#define bfin_read_DMA2_7_START_ADDR()   bfin_readPTR(DMA2_7_START_ADDR)
#define bfin_write_DMA2_7_START_ADDR(val)   bfin_writePTR(DMA2_7_START_ADDR, val)
#define pDMA2_7_X_COUNT   ((uint16_t volatile *)DMA2_7_X_COUNT)
#define bfin_read_DMA2_7_X_COUNT()   bfin_read16(DMA2_7_X_COUNT)
#define bfin_write_DMA2_7_X_COUNT(val)   bfin_write16(DMA2_7_X_COUNT, val)
#define pDMA2_7_Y_COUNT   ((uint16_t volatile *)DMA2_7_Y_COUNT)
#define bfin_read_DMA2_7_Y_COUNT()   bfin_read16(DMA2_7_Y_COUNT)
#define bfin_write_DMA2_7_Y_COUNT(val)   bfin_write16(DMA2_7_Y_COUNT, val)
#define pDMA2_7_X_MODIFY   ((uint16_t volatile *)DMA2_7_X_MODIFY)
#define bfin_read_DMA2_7_X_MODIFY()   bfin_read16(DMA2_7_X_MODIFY)
#define bfin_write_DMA2_7_X_MODIFY(val)   bfin_write16(DMA2_7_X_MODIFY, val)
#define pDMA2_7_Y_MODIFY   ((uint16_t volatile *)DMA2_7_Y_MODIFY)
#define bfin_read_DMA2_7_Y_MODIFY()   bfin_read16(DMA2_7_Y_MODIFY)
#define bfin_write_DMA2_7_Y_MODIFY(val)   bfin_write16(DMA2_7_Y_MODIFY, val)
#define pDMA2_7_CURR_DESC_PTR   ((void * volatile *)DMA2_7_CURR_DESC_PTR)
#define bfin_read_DMA2_7_CURR_DESC_PTR()   bfin_readPTR(DMA2_7_CURR_DESC_PTR)
#define bfin_write_DMA2_7_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
#define pDMA2_7_CURR_ADDR   ((void * volatile *)DMA2_7_CURR_ADDR)
#define bfin_read_DMA2_7_CURR_ADDR()   bfin_readPTR(DMA2_7_CURR_ADDR)
#define bfin_write_DMA2_7_CURR_ADDR(val)   bfin_writePTR(DMA2_7_CURR_ADDR, val)
#define pDMA2_7_CURR_X_COUNT   ((uint16_t volatile *)DMA2_7_CURR_X_COUNT)
#define bfin_read_DMA2_7_CURR_X_COUNT()   bfin_read16(DMA2_7_CURR_X_COUNT)
#define bfin_write_DMA2_7_CURR_X_COUNT(val)   bfin_write16(DMA2_7_CURR_X_COUNT, val)
#define pDMA2_7_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT)
#define bfin_read_DMA2_7_CURR_Y_COUNT()   bfin_read16(DMA2_7_CURR_Y_COUNT)
#define bfin_write_DMA2_7_CURR_Y_COUNT(val)   bfin_write16(DMA2_7_CURR_Y_COUNT, val)
#define pDMA2_7_IRQ_STATUS   ((uint16_t volatile *)DMA2_7_IRQ_STATUS)
#define bfin_read_DMA2_7_IRQ_STATUS()   bfin_read16(DMA2_7_IRQ_STATUS)
#define bfin_write_DMA2_7_IRQ_STATUS(val)   bfin_write16(DMA2_7_IRQ_STATUS, val)
#define pDMA2_7_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP)
#define bfin_read_DMA2_7_PERIPHERAL_MAP()   bfin_read16(DMA2_7_PERIPHERAL_MAP)
#define bfin_write_DMA2_7_PERIPHERAL_MAP(val)   bfin_write16(DMA2_7_PERIPHERAL_MAP, val)
#define pDMA2_8_CONFIG   ((uint16_t volatile *)DMA2_8_CONFIG)
#define bfin_read_DMA2_8_CONFIG()   bfin_read16(DMA2_8_CONFIG)
#define bfin_write_DMA2_8_CONFIG(val)   bfin_write16(DMA2_8_CONFIG, val)
#define pDMA2_8_NEXT_DESC_PTR   ((void * volatile *)DMA2_8_NEXT_DESC_PTR)
#define bfin_read_DMA2_8_NEXT_DESC_PTR()   bfin_readPTR(DMA2_8_NEXT_DESC_PTR)
#define bfin_write_DMA2_8_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
#define pDMA2_8_START_ADDR   ((void * volatile *)DMA2_8_START_ADDR)
#define bfin_read_DMA2_8_START_ADDR()   bfin_readPTR(DMA2_8_START_ADDR)
#define bfin_write_DMA2_8_START_ADDR(val)   bfin_writePTR(DMA2_8_START_ADDR, val)
#define pDMA2_8_X_COUNT   ((uint16_t volatile *)DMA2_8_X_COUNT)
#define bfin_read_DMA2_8_X_COUNT()   bfin_read16(DMA2_8_X_COUNT)
#define bfin_write_DMA2_8_X_COUNT(val)   bfin_write16(DMA2_8_X_COUNT, val)
#define pDMA2_8_Y_COUNT   ((uint16_t volatile *)DMA2_8_Y_COUNT)
#define bfin_read_DMA2_8_Y_COUNT()   bfin_read16(DMA2_8_Y_COUNT)
#define bfin_write_DMA2_8_Y_COUNT(val)   bfin_write16(DMA2_8_Y_COUNT, val)
#define pDMA2_8_X_MODIFY   ((uint16_t volatile *)DMA2_8_X_MODIFY)
#define bfin_read_DMA2_8_X_MODIFY()   bfin_read16(DMA2_8_X_MODIFY)
#define bfin_write_DMA2_8_X_MODIFY(val)   bfin_write16(DMA2_8_X_MODIFY, val)
#define pDMA2_8_Y_MODIFY   ((uint16_t volatile *)DMA2_8_Y_MODIFY)
#define bfin_read_DMA2_8_Y_MODIFY()   bfin_read16(DMA2_8_Y_MODIFY)
#define bfin_write_DMA2_8_Y_MODIFY(val)   bfin_write16(DMA2_8_Y_MODIFY, val)
#define pDMA2_8_CURR_DESC_PTR   ((void * volatile *)DMA2_8_CURR_DESC_PTR)
#define bfin_read_DMA2_8_CURR_DESC_PTR()   bfin_readPTR(DMA2_8_CURR_DESC_PTR)
#define bfin_write_DMA2_8_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
#define pDMA2_8_CURR_ADDR   ((void * volatile *)DMA2_8_CURR_ADDR)
#define bfin_read_DMA2_8_CURR_ADDR()   bfin_readPTR(DMA2_8_CURR_ADDR)
#define bfin_write_DMA2_8_CURR_ADDR(val)   bfin_writePTR(DMA2_8_CURR_ADDR, val)
#define pDMA2_8_CURR_X_COUNT   ((uint16_t volatile *)DMA2_8_CURR_X_COUNT)
#define bfin_read_DMA2_8_CURR_X_COUNT()   bfin_read16(DMA2_8_CURR_X_COUNT)
#define bfin_write_DMA2_8_CURR_X_COUNT(val)   bfin_write16(DMA2_8_CURR_X_COUNT, val)
#define pDMA2_8_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT)
#define bfin_read_DMA2_8_CURR_Y_COUNT()   bfin_read16(DMA2_8_CURR_Y_COUNT)
#define bfin_write_DMA2_8_CURR_Y_COUNT(val)   bfin_write16(DMA2_8_CURR_Y_COUNT, val)
#define pDMA2_8_IRQ_STATUS   ((uint16_t volatile *)DMA2_8_IRQ_STATUS)
#define bfin_read_DMA2_8_IRQ_STATUS()   bfin_read16(DMA2_8_IRQ_STATUS)
#define bfin_write_DMA2_8_IRQ_STATUS(val)   bfin_write16(DMA2_8_IRQ_STATUS, val)
#define pDMA2_8_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP)
#define bfin_read_DMA2_8_PERIPHERAL_MAP()   bfin_read16(DMA2_8_PERIPHERAL_MAP)
#define bfin_write_DMA2_8_PERIPHERAL_MAP(val)   bfin_write16(DMA2_8_PERIPHERAL_MAP, val)
#define pDMA2_9_CONFIG   ((uint16_t volatile *)DMA2_9_CONFIG)
#define bfin_read_DMA2_9_CONFIG()   bfin_read16(DMA2_9_CONFIG)
#define bfin_write_DMA2_9_CONFIG(val)   bfin_write16(DMA2_9_CONFIG, val)
#define pDMA2_9_NEXT_DESC_PTR   ((void * volatile *)DMA2_9_NEXT_DESC_PTR)
#define bfin_read_DMA2_9_NEXT_DESC_PTR()   bfin_readPTR(DMA2_9_NEXT_DESC_PTR)
#define bfin_write_DMA2_9_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
#define pDMA2_9_START_ADDR   ((void * volatile *)DMA2_9_START_ADDR)
#define bfin_read_DMA2_9_START_ADDR()   bfin_readPTR(DMA2_9_START_ADDR)
#define bfin_write_DMA2_9_START_ADDR(val)   bfin_writePTR(DMA2_9_START_ADDR, val)
#define pDMA2_9_X_COUNT   ((uint16_t volatile *)DMA2_9_X_COUNT)
#define bfin_read_DMA2_9_X_COUNT()   bfin_read16(DMA2_9_X_COUNT)
#define bfin_write_DMA2_9_X_COUNT(val)   bfin_write16(DMA2_9_X_COUNT, val)
#define pDMA2_9_Y_COUNT   ((uint16_t volatile *)DMA2_9_Y_COUNT)
#define bfin_read_DMA2_9_Y_COUNT()   bfin_read16(DMA2_9_Y_COUNT)
#define bfin_write_DMA2_9_Y_COUNT(val)   bfin_write16(DMA2_9_Y_COUNT, val)
#define pDMA2_9_X_MODIFY   ((uint16_t volatile *)DMA2_9_X_MODIFY)
#define bfin_read_DMA2_9_X_MODIFY()   bfin_read16(DMA2_9_X_MODIFY)
#define bfin_write_DMA2_9_X_MODIFY(val)   bfin_write16(DMA2_9_X_MODIFY, val)
#define pDMA2_9_Y_MODIFY   ((uint16_t volatile *)DMA2_9_Y_MODIFY)
#define bfin_read_DMA2_9_Y_MODIFY()   bfin_read16(DMA2_9_Y_MODIFY)
#define bfin_write_DMA2_9_Y_MODIFY(val)   bfin_write16(DMA2_9_Y_MODIFY, val)
#define pDMA2_9_CURR_DESC_PTR   ((void * volatile *)DMA2_9_CURR_DESC_PTR)
#define bfin_read_DMA2_9_CURR_DESC_PTR()   bfin_readPTR(DMA2_9_CURR_DESC_PTR)
#define bfin_write_DMA2_9_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
#define pDMA2_9_CURR_ADDR   ((void * volatile *)DMA2_9_CURR_ADDR)
#define bfin_read_DMA2_9_CURR_ADDR()   bfin_readPTR(DMA2_9_CURR_ADDR)
#define bfin_write_DMA2_9_CURR_ADDR(val)   bfin_writePTR(DMA2_9_CURR_ADDR, val)
#define pDMA2_9_CURR_X_COUNT   ((uint16_t volatile *)DMA2_9_CURR_X_COUNT)
#define bfin_read_DMA2_9_CURR_X_COUNT()   bfin_read16(DMA2_9_CURR_X_COUNT)
#define bfin_write_DMA2_9_CURR_X_COUNT(val)   bfin_write16(DMA2_9_CURR_X_COUNT, val)
#define pDMA2_9_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT)
#define bfin_read_DMA2_9_CURR_Y_COUNT()   bfin_read16(DMA2_9_CURR_Y_COUNT)
#define bfin_write_DMA2_9_CURR_Y_COUNT(val)   bfin_write16(DMA2_9_CURR_Y_COUNT, val)
#define pDMA2_9_IRQ_STATUS   ((uint16_t volatile *)DMA2_9_IRQ_STATUS)
#define bfin_read_DMA2_9_IRQ_STATUS()   bfin_read16(DMA2_9_IRQ_STATUS)
#define bfin_write_DMA2_9_IRQ_STATUS(val)   bfin_write16(DMA2_9_IRQ_STATUS, val)
#define pDMA2_9_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP)
#define bfin_read_DMA2_9_PERIPHERAL_MAP()   bfin_read16(DMA2_9_PERIPHERAL_MAP)
#define bfin_write_DMA2_9_PERIPHERAL_MAP(val)   bfin_write16(DMA2_9_PERIPHERAL_MAP, val)
#define pDMA2_10_CONFIG   ((uint16_t volatile *)DMA2_10_CONFIG)
#define bfin_read_DMA2_10_CONFIG()   bfin_read16(DMA2_10_CONFIG)
#define bfin_write_DMA2_10_CONFIG(val)   bfin_write16(DMA2_10_CONFIG, val)
#define pDMA2_10_NEXT_DESC_PTR   ((void * volatile *)DMA2_10_NEXT_DESC_PTR)
#define bfin_read_DMA2_10_NEXT_DESC_PTR()   bfin_readPTR(DMA2_10_NEXT_DESC_PTR)
#define bfin_write_DMA2_10_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
#define pDMA2_10_START_ADDR   ((void * volatile *)DMA2_10_START_ADDR)
#define bfin_read_DMA2_10_START_ADDR()   bfin_readPTR(DMA2_10_START_ADDR)
#define bfin_write_DMA2_10_START_ADDR(val)   bfin_writePTR(DMA2_10_START_ADDR, val)
#define pDMA2_10_X_COUNT   ((uint16_t volatile *)DMA2_10_X_COUNT)
#define bfin_read_DMA2_10_X_COUNT()   bfin_read16(DMA2_10_X_COUNT)
#define bfin_write_DMA2_10_X_COUNT(val)   bfin_write16(DMA2_10_X_COUNT, val)
#define pDMA2_10_Y_COUNT   ((uint16_t volatile *)DMA2_10_Y_COUNT)
#define bfin_read_DMA2_10_Y_COUNT()   bfin_read16(DMA2_10_Y_COUNT)
#define bfin_write_DMA2_10_Y_COUNT(val)   bfin_write16(DMA2_10_Y_COUNT, val)
#define pDMA2_10_X_MODIFY   ((uint16_t volatile *)DMA2_10_X_MODIFY)
#define bfin_read_DMA2_10_X_MODIFY()   bfin_read16(DMA2_10_X_MODIFY)
#define bfin_write_DMA2_10_X_MODIFY(val)   bfin_write16(DMA2_10_X_MODIFY, val)
#define pDMA2_10_Y_MODIFY   ((uint16_t volatile *)DMA2_10_Y_MODIFY)
#define bfin_read_DMA2_10_Y_MODIFY()   bfin_read16(DMA2_10_Y_MODIFY)
#define bfin_write_DMA2_10_Y_MODIFY(val)   bfin_write16(DMA2_10_Y_MODIFY, val)
#define pDMA2_10_CURR_DESC_PTR   ((void * volatile *)DMA2_10_CURR_DESC_PTR)
#define bfin_read_DMA2_10_CURR_DESC_PTR()   bfin_readPTR(DMA2_10_CURR_DESC_PTR)
#define bfin_write_DMA2_10_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
#define pDMA2_10_CURR_ADDR   ((void * volatile *)DMA2_10_CURR_ADDR)
#define bfin_read_DMA2_10_CURR_ADDR()   bfin_readPTR(DMA2_10_CURR_ADDR)
#define bfin_write_DMA2_10_CURR_ADDR(val)   bfin_writePTR(DMA2_10_CURR_ADDR, val)
#define pDMA2_10_CURR_X_COUNT   ((uint16_t volatile *)DMA2_10_CURR_X_COUNT)
#define bfin_read_DMA2_10_CURR_X_COUNT()   bfin_read16(DMA2_10_CURR_X_COUNT)
#define bfin_write_DMA2_10_CURR_X_COUNT(val)   bfin_write16(DMA2_10_CURR_X_COUNT, val)
#define pDMA2_10_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT)
#define bfin_read_DMA2_10_CURR_Y_COUNT()   bfin_read16(DMA2_10_CURR_Y_COUNT)
#define bfin_write_DMA2_10_CURR_Y_COUNT(val)   bfin_write16(DMA2_10_CURR_Y_COUNT, val)
#define pDMA2_10_IRQ_STATUS   ((uint16_t volatile *)DMA2_10_IRQ_STATUS)
#define bfin_read_DMA2_10_IRQ_STATUS()   bfin_read16(DMA2_10_IRQ_STATUS)
#define bfin_write_DMA2_10_IRQ_STATUS(val)   bfin_write16(DMA2_10_IRQ_STATUS, val)
#define pDMA2_10_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP)
#define bfin_read_DMA2_10_PERIPHERAL_MAP()   bfin_read16(DMA2_10_PERIPHERAL_MAP)
#define bfin_write_DMA2_10_PERIPHERAL_MAP(val)   bfin_write16(DMA2_10_PERIPHERAL_MAP, val)
#define pDMA2_11_CONFIG   ((uint16_t volatile *)DMA2_11_CONFIG)
#define bfin_read_DMA2_11_CONFIG()   bfin_read16(DMA2_11_CONFIG)
#define bfin_write_DMA2_11_CONFIG(val)   bfin_write16(DMA2_11_CONFIG, val)
#define pDMA2_11_NEXT_DESC_PTR   ((void * volatile *)DMA2_11_NEXT_DESC_PTR)
#define bfin_read_DMA2_11_NEXT_DESC_PTR()   bfin_readPTR(DMA2_11_NEXT_DESC_PTR)
#define bfin_write_DMA2_11_NEXT_DESC_PTR(val)   bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
#define pDMA2_11_START_ADDR   ((void * volatile *)DMA2_11_START_ADDR)
#define bfin_read_DMA2_11_START_ADDR()   bfin_readPTR(DMA2_11_START_ADDR)
#define bfin_write_DMA2_11_START_ADDR(val)   bfin_writePTR(DMA2_11_START_ADDR, val)
#define pDMA2_11_X_COUNT   ((uint16_t volatile *)DMA2_11_X_COUNT)
#define bfin_read_DMA2_11_X_COUNT()   bfin_read16(DMA2_11_X_COUNT)
#define bfin_write_DMA2_11_X_COUNT(val)   bfin_write16(DMA2_11_X_COUNT, val)
#define pDMA2_11_Y_COUNT   ((uint16_t volatile *)DMA2_11_Y_COUNT)
#define bfin_read_DMA2_11_Y_COUNT()   bfin_read16(DMA2_11_Y_COUNT)
#define bfin_write_DMA2_11_Y_COUNT(val)   bfin_write16(DMA2_11_Y_COUNT, val)
#define pDMA2_11_X_MODIFY   ((uint16_t volatile *)DMA2_11_X_MODIFY)
#define bfin_read_DMA2_11_X_MODIFY()   bfin_read16(DMA2_11_X_MODIFY)
#define bfin_write_DMA2_11_X_MODIFY(val)   bfin_write16(DMA2_11_X_MODIFY, val)
#define pDMA2_11_Y_MODIFY   ((uint16_t volatile *)DMA2_11_Y_MODIFY)
#define bfin_read_DMA2_11_Y_MODIFY()   bfin_read16(DMA2_11_Y_MODIFY)
#define bfin_write_DMA2_11_Y_MODIFY(val)   bfin_write16(DMA2_11_Y_MODIFY, val)
#define pDMA2_11_CURR_DESC_PTR   ((void * volatile *)DMA2_11_CURR_DESC_PTR)
#define bfin_read_DMA2_11_CURR_DESC_PTR()   bfin_readPTR(DMA2_11_CURR_DESC_PTR)
#define bfin_write_DMA2_11_CURR_DESC_PTR(val)   bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
#define pDMA2_11_CURR_ADDR   ((void * volatile *)DMA2_11_CURR_ADDR)
#define bfin_read_DMA2_11_CURR_ADDR()   bfin_readPTR(DMA2_11_CURR_ADDR)
#define bfin_write_DMA2_11_CURR_ADDR(val)   bfin_writePTR(DMA2_11_CURR_ADDR, val)
#define pDMA2_11_CURR_X_COUNT   ((uint16_t volatile *)DMA2_11_CURR_X_COUNT)
#define bfin_read_DMA2_11_CURR_X_COUNT()   bfin_read16(DMA2_11_CURR_X_COUNT)
#define bfin_write_DMA2_11_CURR_X_COUNT(val)   bfin_write16(DMA2_11_CURR_X_COUNT, val)
#define pDMA2_11_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT)
#define bfin_read_DMA2_11_CURR_Y_COUNT()   bfin_read16(DMA2_11_CURR_Y_COUNT)
#define bfin_write_DMA2_11_CURR_Y_COUNT(val)   bfin_write16(DMA2_11_CURR_Y_COUNT, val)
#define pDMA2_11_IRQ_STATUS   ((uint16_t volatile *)DMA2_11_IRQ_STATUS)
#define bfin_read_DMA2_11_IRQ_STATUS()   bfin_read16(DMA2_11_IRQ_STATUS)
#define bfin_write_DMA2_11_IRQ_STATUS(val)   bfin_write16(DMA2_11_IRQ_STATUS, val)
#define pDMA2_11_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP)
#define bfin_read_DMA2_11_PERIPHERAL_MAP()   bfin_read16(DMA2_11_PERIPHERAL_MAP)
#define bfin_write_DMA2_11_PERIPHERAL_MAP(val)   bfin_write16(DMA2_11_PERIPHERAL_MAP, val)
#define pIMDMA_S0_CONFIG   ((uint16_t volatile *)IMDMA_S0_CONFIG)
#define bfin_read_IMDMA_S0_CONFIG()   bfin_read16(IMDMA_S0_CONFIG)
#define bfin_write_IMDMA_S0_CONFIG(val)   bfin_write16(IMDMA_S0_CONFIG, val)
#define pIMDMA_S0_NEXT_DESC_PTR   ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR)
#define bfin_read_IMDMA_S0_NEXT_DESC_PTR()   bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)
#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val)   bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
#define pIMDMA_S0_START_ADDR   ((void * volatile *)IMDMA_S0_START_ADDR)
#define bfin_read_IMDMA_S0_START_ADDR()   bfin_readPTR(IMDMA_S0_START_ADDR)
#define bfin_write_IMDMA_S0_START_ADDR(val)   bfin_writePTR(IMDMA_S0_START_ADDR, val)
#define pIMDMA_S0_X_COUNT   ((uint16_t volatile *)IMDMA_S0_X_COUNT)
#define bfin_read_IMDMA_S0_X_COUNT()   bfin_read16(IMDMA_S0_X_COUNT)
#define bfin_write_IMDMA_S0_X_COUNT(val)   bfin_write16(IMDMA_S0_X_COUNT, val)
#define pIMDMA_S0_Y_COUNT   ((uint16_t volatile *)IMDMA_S0_Y_COUNT)
#define bfin_read_IMDMA_S0_Y_COUNT()   bfin_read16(IMDMA_S0_Y_COUNT)
#define bfin_write_IMDMA_S0_Y_COUNT(val)   bfin_write16(IMDMA_S0_Y_COUNT, val)
#define pIMDMA_S0_X_MODIFY   ((uint16_t volatile *)IMDMA_S0_X_MODIFY)
#define bfin_read_IMDMA_S0_X_MODIFY()   bfin_read16(IMDMA_S0_X_MODIFY)
#define bfin_write_IMDMA_S0_X_MODIFY(val)   bfin_write16(IMDMA_S0_X_MODIFY, val)
#define pIMDMA_S0_Y_MODIFY   ((uint16_t volatile *)IMDMA_S0_Y_MODIFY)
#define bfin_read_IMDMA_S0_Y_MODIFY()   bfin_read16(IMDMA_S0_Y_MODIFY)
#define bfin_write_IMDMA_S0_Y_MODIFY(val)   bfin_write16(IMDMA_S0_Y_MODIFY, val)
#define pIMDMA_S0_CURR_DESC_PTR   ((void * volatile *)IMDMA_S0_CURR_DESC_PTR)
#define bfin_read_IMDMA_S0_CURR_DESC_PTR()   bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)
#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val)   bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
#define pIMDMA_S0_CURR_ADDR   ((void * volatile *)IMDMA_S0_CURR_ADDR)
#define bfin_read_IMDMA_S0_CURR_ADDR()   bfin_readPTR(IMDMA_S0_CURR_ADDR)
#define bfin_write_IMDMA_S0_CURR_ADDR(val)   bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
#define pIMDMA_S0_CURR_X_COUNT   ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT)
#define bfin_read_IMDMA_S0_CURR_X_COUNT()   bfin_read16(IMDMA_S0_CURR_X_COUNT)
#define bfin_write_IMDMA_S0_CURR_X_COUNT(val)   bfin_write16(IMDMA_S0_CURR_X_COUNT, val)
#define pIMDMA_S0_CURR_Y_COUNT   ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT)
#define bfin_read_IMDMA_S0_CURR_Y_COUNT()   bfin_read16(IMDMA_S0_CURR_Y_COUNT)
#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val)   bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)
#define pIMDMA_S0_IRQ_STATUS   ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS)
#define bfin_read_IMDMA_S0_IRQ_STATUS()   bfin_read16(IMDMA_S0_IRQ_STATUS)
#define bfin_write_IMDMA_S0_IRQ_STATUS(val)   bfin_write16(IMDMA_S0_IRQ_STATUS, val)
#define pIMDMA_D0_CONFIG   ((uint16_t volatile *)IMDMA_D0_CONFIG)
#define bfin_read_IMDMA_D0_CONFIG()   bfin_read16(IMDMA_D0_CONFIG)
#define bfin_write_IMDMA_D0_CONFIG(val)   bfin_write16(IMDMA_D0_CONFIG, val)
#define pIMDMA_D0_NEXT_DESC_PTR   ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR)
#define bfin_read_IMDMA_D0_NEXT_DESC_PTR()   bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)
#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val)   bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
#define pIMDMA_D0_START_ADDR   ((void * volatile *)IMDMA_D0_START_ADDR)
#define bfin_read_IMDMA_D0_START_ADDR()   bfin_readPTR(IMDMA_D0_START_ADDR)
#define bfin_write_IMDMA_D0_START_ADDR(val)   bfin_writePTR(IMDMA_D0_START_ADDR, val)
#define pIMDMA_D0_X_COUNT   ((uint16_t volatile *)IMDMA_D0_X_COUNT)
#define bfin_read_IMDMA_D0_X_COUNT()   bfin_read16(IMDMA_D0_X_COUNT)
#define bfin_write_IMDMA_D0_X_COUNT(val)   bfin_write16(IMDMA_D0_X_COUNT, val)
#define pIMDMA_D0_Y_COUNT   ((uint16_t volatile *)IMDMA_D0_Y_COUNT)
#define bfin_read_IMDMA_D0_Y_COUNT()   bfin_read16(IMDMA_D0_Y_COUNT)
#define bfin_write_IMDMA_D0_Y_COUNT(val)   bfin_write16(IMDMA_D0_Y_COUNT, val)
#define pIMDMA_D0_X_MODIFY   ((uint16_t volatile *)IMDMA_D0_X_MODIFY)
#define bfin_read_IMDMA_D0_X_MODIFY()   bfin_read16(IMDMA_D0_X_MODIFY)
#define bfin_write_IMDMA_D0_X_MODIFY(val)   bfin_write16(IMDMA_D0_X_MODIFY, val)
#define pIMDMA_D0_Y_MODIFY   ((uint16_t volatile *)IMDMA_D0_Y_MODIFY)
#define bfin_read_IMDMA_D0_Y_MODIFY()   bfin_read16(IMDMA_D0_Y_MODIFY)
#define bfin_write_IMDMA_D0_Y_MODIFY(val)   bfin_write16(IMDMA_D0_Y_MODIFY, val)
#define pIMDMA_D0_CURR_DESC_PTR   ((void * volatile *)IMDMA_D0_CURR_DESC_PTR)
#define bfin_read_IMDMA_D0_CURR_DESC_PTR()   bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)
#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val)   bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
#define pIMDMA_D0_CURR_ADDR   ((void * volatile *)IMDMA_D0_CURR_ADDR)
#define bfin_read_IMDMA_D0_CURR_ADDR()   bfin_readPTR(IMDMA_D0_CURR_ADDR)
#define bfin_write_IMDMA_D0_CURR_ADDR(val)   bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
#define pIMDMA_D0_CURR_X_COUNT   ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT)
#define bfin_read_IMDMA_D0_CURR_X_COUNT()   bfin_read16(IMDMA_D0_CURR_X_COUNT)
#define bfin_write_IMDMA_D0_CURR_X_COUNT(val)   bfin_write16(IMDMA_D0_CURR_X_COUNT, val)
#define pIMDMA_D0_CURR_Y_COUNT   ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT)
#define bfin_read_IMDMA_D0_CURR_Y_COUNT()   bfin_read16(IMDMA_D0_CURR_Y_COUNT)
#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val)   bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)
#define pIMDMA_D0_IRQ_STATUS   ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS)
#define bfin_read_IMDMA_D0_IRQ_STATUS()   bfin_read16(IMDMA_D0_IRQ_STATUS)
#define bfin_write_IMDMA_D0_IRQ_STATUS(val)   bfin_write16(IMDMA_D0_IRQ_STATUS, val)
#define pIMDMA_S1_CONFIG   ((uint16_t volatile *)IMDMA_S1_CONFIG)
#define bfin_read_IMDMA_S1_CONFIG()   bfin_read16(IMDMA_S1_CONFIG)
#define bfin_write_IMDMA_S1_CONFIG(val)   bfin_write16(IMDMA_S1_CONFIG, val)
#define pIMDMA_S1_NEXT_DESC_PTR   ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR)
#define bfin_read_IMDMA_S1_NEXT_DESC_PTR()   bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)
#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val)   bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
#define pIMDMA_S1_START_ADDR   ((void * volatile *)IMDMA_S1_START_ADDR)
#define bfin_read_IMDMA_S1_START_ADDR()   bfin_readPTR(IMDMA_S1_START_ADDR)
#define bfin_write_IMDMA_S1_START_ADDR(val)   bfin_writePTR(IMDMA_S1_START_ADDR, val)
#define pIMDMA_S1_X_COUNT   ((uint16_t volatile *)IMDMA_S1_X_COUNT)
#define bfin_read_IMDMA_S1_X_COUNT()   bfin_read16(IMDMA_S1_X_COUNT)
#define bfin_write_IMDMA_S1_X_COUNT(val)   bfin_write16(IMDMA_S1_X_COUNT, val)
#define pIMDMA_S1_Y_COUNT   ((uint16_t volatile *)IMDMA_S1_Y_COUNT)
#define bfin_read_IMDMA_S1_Y_COUNT()   bfin_read16(IMDMA_S1_Y_COUNT)
#define bfin_write_IMDMA_S1_Y_COUNT(val)   bfin_write16(IMDMA_S1_Y_COUNT, val)
#define pIMDMA_S1_X_MODIFY   ((uint16_t volatile *)IMDMA_S1_X_MODIFY)
#define bfin_read_IMDMA_S1_X_MODIFY()   bfin_read16(IMDMA_S1_X_MODIFY)
#define bfin_write_IMDMA_S1_X_MODIFY(val)   bfin_write16(IMDMA_S1_X_MODIFY, val)
#define pIMDMA_S1_Y_MODIFY   ((uint16_t volatile *)IMDMA_S1_Y_MODIFY)
#define bfin_read_IMDMA_S1_Y_MODIFY()   bfin_read16(IMDMA_S1_Y_MODIFY)
#define bfin_write_IMDMA_S1_Y_MODIFY(val)   bfin_write16(IMDMA_S1_Y_MODIFY, val)
#define pIMDMA_S1_CURR_DESC_PTR   ((void * volatile *)IMDMA_S1_CURR_DESC_PTR)
#define bfin_read_IMDMA_S1_CURR_DESC_PTR()   bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)
#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val)   bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
#define pIMDMA_S1_CURR_ADDR   ((void * volatile *)IMDMA_S1_CURR_ADDR)
#define bfin_read_IMDMA_S1_CURR_ADDR()   bfin_readPTR(IMDMA_S1_CURR_ADDR)
#define bfin_write_IMDMA_S1_CURR_ADDR(val)   bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
#define pIMDMA_S1_CURR_X_COUNT   ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT)
#define bfin_read_IMDMA_S1_CURR_X_COUNT()   bfin_read16(IMDMA_S1_CURR_X_COUNT)
#define bfin_write_IMDMA_S1_CURR_X_COUNT(val)   bfin_write16(IMDMA_S1_CURR_X_COUNT, val)
#define pIMDMA_S1_CURR_Y_COUNT   ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT)
#define bfin_read_IMDMA_S1_CURR_Y_COUNT()   bfin_read16(IMDMA_S1_CURR_Y_COUNT)
#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val)   bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)
#define pIMDMA_S1_IRQ_STATUS   ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS)
#define bfin_read_IMDMA_S1_IRQ_STATUS()   bfin_read16(IMDMA_S1_IRQ_STATUS)
#define bfin_write_IMDMA_S1_IRQ_STATUS(val)   bfin_write16(IMDMA_S1_IRQ_STATUS, val)
#define pIMDMA_D1_CONFIG   ((uint16_t volatile *)IMDMA_D1_CONFIG)
#define bfin_read_IMDMA_D1_CONFIG()   bfin_read16(IMDMA_D1_CONFIG)
#define bfin_write_IMDMA_D1_CONFIG(val)   bfin_write16(IMDMA_D1_CONFIG, val)
#define pIMDMA_D1_NEXT_DESC_PTR   ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR)
#define bfin_read_IMDMA_D1_NEXT_DESC_PTR()   bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)
#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val)   bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
#define pIMDMA_D1_START_ADDR   ((void * volatile *)IMDMA_D1_START_ADDR)
#define bfin_read_IMDMA_D1_START_ADDR()   bfin_readPTR(IMDMA_D1_START_ADDR)
#define bfin_write_IMDMA_D1_START_ADDR(val)   bfin_writePTR(IMDMA_D1_START_ADDR, val)
#define pIMDMA_D1_X_COUNT   ((uint16_t volatile *)IMDMA_D1_X_COUNT)
#define bfin_read_IMDMA_D1_X_COUNT()   bfin_read16(IMDMA_D1_X_COUNT)
#define bfin_write_IMDMA_D1_X_COUNT(val)   bfin_write16(IMDMA_D1_X_COUNT, val)
#define pIMDMA_D1_Y_COUNT   ((uint16_t volatile *)IMDMA_D1_Y_COUNT)
#define bfin_read_IMDMA_D1_Y_COUNT()   bfin_read16(IMDMA_D1_Y_COUNT)
#define bfin_write_IMDMA_D1_Y_COUNT(val)   bfin_write16(IMDMA_D1_Y_COUNT, val)
#define pIMDMA_D1_X_MODIFY   ((uint16_t volatile *)IMDMA_D1_X_MODIFY)
#define bfin_read_IMDMA_D1_X_MODIFY()   bfin_read16(IMDMA_D1_X_MODIFY)
#define bfin_write_IMDMA_D1_X_MODIFY(val)   bfin_write16(IMDMA_D1_X_MODIFY, val)
#define pIMDMA_D1_Y_MODIFY   ((uint16_t volatile *)IMDMA_D1_Y_MODIFY)
#define bfin_read_IMDMA_D1_Y_MODIFY()   bfin_read16(IMDMA_D1_Y_MODIFY)
#define bfin_write_IMDMA_D1_Y_MODIFY(val)   bfin_write16(IMDMA_D1_Y_MODIFY, val)
#define pIMDMA_D1_CURR_DESC_PTR   ((void * volatile *)IMDMA_D1_CURR_DESC_PTR)
#define bfin_read_IMDMA_D1_CURR_DESC_PTR()   bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)
#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val)   bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
#define pIMDMA_D1_CURR_ADDR   ((void * volatile *)IMDMA_D1_CURR_ADDR)
#define bfin_read_IMDMA_D1_CURR_ADDR()   bfin_readPTR(IMDMA_D1_CURR_ADDR)
#define bfin_write_IMDMA_D1_CURR_ADDR(val)   bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
#define pIMDMA_D1_CURR_X_COUNT   ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT)
#define bfin_read_IMDMA_D1_CURR_X_COUNT()   bfin_read16(IMDMA_D1_CURR_X_COUNT)
#define bfin_write_IMDMA_D1_CURR_X_COUNT(val)   bfin_write16(IMDMA_D1_CURR_X_COUNT, val)
#define pIMDMA_D1_CURR_Y_COUNT   ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT)
#define bfin_read_IMDMA_D1_CURR_Y_COUNT()   bfin_read16(IMDMA_D1_CURR_Y_COUNT)
#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val)   bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)
#define pIMDMA_D1_IRQ_STATUS   ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS)
#define bfin_read_IMDMA_D1_IRQ_STATUS()   bfin_read16(IMDMA_D1_IRQ_STATUS)
#define bfin_write_IMDMA_D1_IRQ_STATUS(val)   bfin_write16(IMDMA_D1_IRQ_STATUS, val)
#define pMDMA1_S0_CONFIG   ((uint16_t volatile *)MDMA1_S0_CONFIG)
#define bfin_read_MDMA1_S0_CONFIG()   bfin_read16(MDMA1_S0_CONFIG)
#define bfin_write_MDMA1_S0_CONFIG(val)   bfin_write16(MDMA1_S0_CONFIG, val)
#define pMDMA1_S0_NEXT_DESC_PTR   ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
#define bfin_read_MDMA1_S0_NEXT_DESC_PTR()   bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val)   bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
#define pMDMA1_S0_START_ADDR   ((void * volatile *)MDMA1_S0_START_ADDR)
#define bfin_read_MDMA1_S0_START_ADDR()   bfin_readPTR(MDMA1_S0_START_ADDR)
#define bfin_write_MDMA1_S0_START_ADDR(val)   bfin_writePTR(MDMA1_S0_START_ADDR, val)
#define pMDMA1_S0_X_COUNT   ((uint16_t volatile *)MDMA1_S0_X_COUNT)
#define bfin_read_MDMA1_S0_X_COUNT()   bfin_read16(MDMA1_S0_X_COUNT)
#define bfin_write_MDMA1_S0_X_COUNT(val)   bfin_write16(MDMA1_S0_X_COUNT, val)
#define pMDMA1_S0_Y_COUNT   ((uint16_t volatile *)MDMA1_S0_Y_COUNT)
#define bfin_read_MDMA1_S0_Y_COUNT()   bfin_read16(MDMA1_S0_Y_COUNT)
#define bfin_write_MDMA1_S0_Y_COUNT(val)   bfin_write16(MDMA1_S0_Y_COUNT, val)
#define pMDMA1_S0_X_MODIFY   ((uint16_t volatile *)MDMA1_S0_X_MODIFY)
#define bfin_read_MDMA1_S0_X_MODIFY()   bfin_read16(MDMA1_S0_X_MODIFY)
#define bfin_write_MDMA1_S0_X_MODIFY(val)   bfin_write16(MDMA1_S0_X_MODIFY, val)
#define pMDMA1_S0_Y_MODIFY   ((uint16_t volatile *)MDMA1_S0_Y_MODIFY)
#define bfin_read_MDMA1_S0_Y_MODIFY()   bfin_read16(MDMA1_S0_Y_MODIFY)
#define bfin_write_MDMA1_S0_Y_MODIFY(val)   bfin_write16(MDMA1_S0_Y_MODIFY, val)
#define pMDMA1_S0_CURR_DESC_PTR   ((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
#define bfin_read_MDMA1_S0_CURR_DESC_PTR()   bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val)   bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
#define pMDMA1_S0_CURR_ADDR   ((void * volatile *)MDMA1_S0_CURR_ADDR)
#define bfin_read_MDMA1_S0_CURR_ADDR()   bfin_readPTR(MDMA1_S0_CURR_ADDR)
#define bfin_write_MDMA1_S0_CURR_ADDR(val)   bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
#define pMDMA1_S0_CURR_X_COUNT   ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT)
#define bfin_read_MDMA1_S0_CURR_X_COUNT()   bfin_read16(MDMA1_S0_CURR_X_COUNT)
#define bfin_write_MDMA1_S0_CURR_X_COUNT(val)   bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
#define pMDMA1_S0_CURR_Y_COUNT   ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT)
#define bfin_read_MDMA1_S0_CURR_Y_COUNT()   bfin_read16(MDMA1_S0_CURR_Y_COUNT)
#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val)   bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
#define pMDMA1_S0_IRQ_STATUS   ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS)
#define bfin_read_MDMA1_S0_IRQ_STATUS()   bfin_read16(MDMA1_S0_IRQ_STATUS)
#define bfin_write_MDMA1_S0_IRQ_STATUS(val)   bfin_write16(MDMA1_S0_IRQ_STATUS, val)
#define pMDMA1_S0_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP)
#define bfin_read_MDMA1_S0_PERIPHERAL_MAP()   bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val)   bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
#define pMDMA1_D0_CONFIG   ((uint16_t volatile *)MDMA1_D0_CONFIG)
#define bfin_read_MDMA1_D0_CONFIG()   bfin_read16(MDMA1_D0_CONFIG)
#define bfin_write_MDMA1_D0_CONFIG(val)   bfin_write16(MDMA1_D0_CONFIG, val)
#define pMDMA1_D0_NEXT_DESC_PTR   ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
#define bfin_read_MDMA1_D0_NEXT_DESC_PTR()   bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val)   bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
#define pMDMA1_D0_START_ADDR   ((void * volatile *)MDMA1_D0_START_ADDR)
#define bfin_read_MDMA1_D0_START_ADDR()   bfin_readPTR(MDMA1_D0_START_ADDR)
#define bfin_write_MDMA1_D0_START_ADDR(val)   bfin_writePTR(MDMA1_D0_START_ADDR, val)
#define pMDMA1_D0_X_COUNT   ((uint16_t volatile *)MDMA1_D0_X_COUNT)
#define bfin_read_MDMA1_D0_X_COUNT()   bfin_read16(MDMA1_D0_X_COUNT)
#define bfin_write_MDMA1_D0_X_COUNT(val)   bfin_write16(MDMA1_D0_X_COUNT, val)
#define pMDMA1_D0_Y_COUNT   ((uint16_t volatile *)MDMA1_D0_Y_COUNT)
#define bfin_read_MDMA1_D0_Y_COUNT()   bfin_read16(MDMA1_D0_Y_COUNT)
#define bfin_write_MDMA1_D0_Y_COUNT(val)   bfin_write16(MDMA1_D0_Y_COUNT, val)
#define pMDMA1_D0_X_MODIFY   ((uint16_t volatile *)MDMA1_D0_X_MODIFY)
#define bfin_read_MDMA1_D0_X_MODIFY()   bfin_read16(MDMA1_D0_X_MODIFY)
#define bfin_write_MDMA1_D0_X_MODIFY(val)   bfin_write16(MDMA1_D0_X_MODIFY, val)
#define pMDMA1_D0_Y_MODIFY   ((uint16_t volatile *)MDMA1_D0_Y_MODIFY)
#define bfin_read_MDMA1_D0_Y_MODIFY()   bfin_read16(MDMA1_D0_Y_MODIFY)
#define bfin_write_MDMA1_D0_Y_MODIFY(val)   bfin_write16(MDMA1_D0_Y_MODIFY, val)
#define pMDMA1_D0_CURR_DESC_PTR   ((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
#define bfin_read_MDMA1_D0_CURR_DESC_PTR()   bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val)   bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
#define pMDMA1_D0_CURR_ADDR   ((void * volatile *)MDMA1_D0_CURR_ADDR)
#define bfin_read_MDMA1_D0_CURR_ADDR()   bfin_readPTR(MDMA1_D0_CURR_ADDR)
#define bfin_write_MDMA1_D0_CURR_ADDR(val)   bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
#define pMDMA1_D0_CURR_X_COUNT   ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT)
#define bfin_read_MDMA1_D0_CURR_X_COUNT()   bfin_read16(MDMA1_D0_CURR_X_COUNT)
#define bfin_write_MDMA1_D0_CURR_X_COUNT(val)   bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
#define pMDMA1_D0_CURR_Y_COUNT   ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT)
#define bfin_read_MDMA1_D0_CURR_Y_COUNT()   bfin_read16(MDMA1_D0_CURR_Y_COUNT)
#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val)   bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
#define pMDMA1_D0_IRQ_STATUS   ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
#define bfin_read_MDMA1_D0_IRQ_STATUS()   bfin_read16(MDMA1_D0_IRQ_STATUS)
#define bfin_write_MDMA1_D0_IRQ_STATUS(val)   bfin_write16(MDMA1_D0_IRQ_STATUS, val)
#define pMDMA1_D0_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP)
#define bfin_read_MDMA1_D0_PERIPHERAL_MAP()   bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val)   bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
#define pMDMA1_S1_CONFIG   ((uint16_t volatile *)MDMA1_S1_CONFIG)
#define bfin_read_MDMA1_S1_CONFIG()   bfin_read16(MDMA1_S1_CONFIG)
#define bfin_write_MDMA1_S1_CONFIG(val)   bfin_write16(MDMA1_S1_CONFIG, val)
#define pMDMA1_S1_NEXT_DESC_PTR   ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
#define bfin_read_MDMA1_S1_NEXT_DESC_PTR()   bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val)   bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
#define pMDMA1_S1_START_ADDR   ((void * volatile *)MDMA1_S1_START_ADDR)
#define bfin_read_MDMA1_S1_START_ADDR()   bfin_readPTR(MDMA1_S1_START_ADDR)
#define bfin_write_MDMA1_S1_START_ADDR(val)   bfin_writePTR(MDMA1_S1_START_ADDR, val)
#define pMDMA1_S1_X_COUNT   ((uint16_t volatile *)MDMA1_S1_X_COUNT)
#define bfin_read_MDMA1_S1_X_COUNT()   bfin_read16(MDMA1_S1_X_COUNT)
#define bfin_write_MDMA1_S1_X_COUNT(val)   bfin_write16(MDMA1_S1_X_COUNT, val)
#define pMDMA1_S1_Y_COUNT   ((uint16_t volatile *)MDMA1_S1_Y_COUNT)
#define bfin_read_MDMA1_S1_Y_COUNT()   bfin_read16(MDMA1_S1_Y_COUNT)
#define bfin_write_MDMA1_S1_Y_COUNT(val)   bfin_write16(MDMA1_S1_Y_COUNT, val)
#define pMDMA1_S1_X_MODIFY   ((uint16_t volatile *)MDMA1_S1_X_MODIFY)
#define bfin_read_MDMA1_S1_X_MODIFY()   bfin_read16(MDMA1_S1_X_MODIFY)
#define bfin_write_MDMA1_S1_X_MODIFY(val)   bfin_write16(MDMA1_S1_X_MODIFY, val)
#define pMDMA1_S1_Y_MODIFY   ((uint16_t volatile *)MDMA1_S1_Y_MODIFY)
#define bfin_read_MDMA1_S1_Y_MODIFY()   bfin_read16(MDMA1_S1_Y_MODIFY)
#define bfin_write_MDMA1_S1_Y_MODIFY(val)   bfin_write16(MDMA1_S1_Y_MODIFY, val)
#define pMDMA1_S1_CURR_DESC_PTR   ((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
#define bfin_read_MDMA1_S1_CURR_DESC_PTR()   bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val)   bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
#define pMDMA1_S1_CURR_ADDR   ((void * volatile *)MDMA1_S1_CURR_ADDR)
#define bfin_read_MDMA1_S1_CURR_ADDR()   bfin_readPTR(MDMA1_S1_CURR_ADDR)
#define bfin_write_MDMA1_S1_CURR_ADDR(val)   bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
#define pMDMA1_S1_CURR_X_COUNT   ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT)
#define bfin_read_MDMA1_S1_CURR_X_COUNT()   bfin_read16(MDMA1_S1_CURR_X_COUNT)
#define bfin_write_MDMA1_S1_CURR_X_COUNT(val)   bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
#define pMDMA1_S1_CURR_Y_COUNT   ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT)
#define bfin_read_MDMA1_S1_CURR_Y_COUNT()   bfin_read16(MDMA1_S1_CURR_Y_COUNT)
#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val)   bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
#define pMDMA1_S1_IRQ_STATUS   ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS)
#define bfin_read_MDMA1_S1_IRQ_STATUS()   bfin_read16(MDMA1_S1_IRQ_STATUS)
#define bfin_write_MDMA1_S1_IRQ_STATUS(val)   bfin_write16(MDMA1_S1_IRQ_STATUS, val)
#define pMDMA1_S1_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP)
#define bfin_read_MDMA1_S1_PERIPHERAL_MAP()   bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val)   bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
#define pMDMA1_D1_CONFIG   ((uint16_t volatile *)MDMA1_D1_CONFIG)
#define bfin_read_MDMA1_D1_CONFIG()   bfin_read16(MDMA1_D1_CONFIG)
#define bfin_write_MDMA1_D1_CONFIG(val)   bfin_write16(MDMA1_D1_CONFIG, val)
#define pMDMA1_D1_NEXT_DESC_PTR   ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
#define bfin_read_MDMA1_D1_NEXT_DESC_PTR()   bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val)   bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
#define pMDMA1_D1_START_ADDR   ((void * volatile *)MDMA1_D1_START_ADDR)
#define bfin_read_MDMA1_D1_START_ADDR()   bfin_readPTR(MDMA1_D1_START_ADDR)
#define bfin_write_MDMA1_D1_START_ADDR(val)   bfin_writePTR(MDMA1_D1_START_ADDR, val)
#define pMDMA1_D1_X_COUNT   ((uint16_t volatile *)MDMA1_D1_X_COUNT)
#define bfin_read_MDMA1_D1_X_COUNT()   bfin_read16(MDMA1_D1_X_COUNT)
#define bfin_write_MDMA1_D1_X_COUNT(val)   bfin_write16(MDMA1_D1_X_COUNT, val)
#define pMDMA1_D1_Y_COUNT   ((uint16_t volatile *)MDMA1_D1_Y_COUNT)
#define bfin_read_MDMA1_D1_Y_COUNT()   bfin_read16(MDMA1_D1_Y_COUNT)
#define bfin_write_MDMA1_D1_Y_COUNT(val)   bfin_write16(MDMA1_D1_Y_COUNT, val)
#define pMDMA1_D1_X_MODIFY   ((uint16_t volatile *)MDMA1_D1_X_MODIFY)
#define bfin_read_MDMA1_D1_X_MODIFY()   bfin_read16(MDMA1_D1_X_MODIFY)
#define bfin_write_MDMA1_D1_X_MODIFY(val)   bfin_write16(MDMA1_D1_X_MODIFY, val)
#define pMDMA1_D1_Y_MODIFY   ((uint16_t volatile *)MDMA1_D1_Y_MODIFY)
#define bfin_read_MDMA1_D1_Y_MODIFY()   bfin_read16(MDMA1_D1_Y_MODIFY)
#define bfin_write_MDMA1_D1_Y_MODIFY(val)   bfin_write16(MDMA1_D1_Y_MODIFY, val)
#define pMDMA1_D1_CURR_DESC_PTR   ((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
#define bfin_read_MDMA1_D1_CURR_DESC_PTR()   bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val)   bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
#define pMDMA1_D1_CURR_ADDR   ((void * volatile *)MDMA1_D1_CURR_ADDR)
#define bfin_read_MDMA1_D1_CURR_ADDR()   bfin_readPTR(MDMA1_D1_CURR_ADDR)
#define bfin_write_MDMA1_D1_CURR_ADDR(val)   bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
#define pMDMA1_D1_CURR_X_COUNT   ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT)
#define bfin_read_MDMA1_D1_CURR_X_COUNT()   bfin_read16(MDMA1_D1_CURR_X_COUNT)
#define bfin_write_MDMA1_D1_CURR_X_COUNT(val)   bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
#define pMDMA1_D1_CURR_Y_COUNT   ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT)
#define bfin_read_MDMA1_D1_CURR_Y_COUNT()   bfin_read16(MDMA1_D1_CURR_Y_COUNT)
#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val)   bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
#define pMDMA1_D1_IRQ_STATUS   ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS)
#define bfin_read_MDMA1_D1_IRQ_STATUS()   bfin_read16(MDMA1_D1_IRQ_STATUS)
#define bfin_write_MDMA1_D1_IRQ_STATUS(val)   bfin_write16(MDMA1_D1_IRQ_STATUS, val)
#define pMDMA1_D1_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP)
#define bfin_read_MDMA1_D1_PERIPHERAL_MAP()   bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val)   bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
#define pMDMA2_S0_CONFIG   ((uint16_t volatile *)MDMA2_S0_CONFIG)
#define bfin_read_MDMA2_S0_CONFIG()   bfin_read16(MDMA2_S0_CONFIG)
#define bfin_write_MDMA2_S0_CONFIG(val)   bfin_write16(MDMA2_S0_CONFIG, val)
#define pMDMA2_S0_NEXT_DESC_PTR   ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR)
#define bfin_read_MDMA2_S0_NEXT_DESC_PTR()   bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val)   bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
#define pMDMA2_S0_START_ADDR   ((void * volatile *)MDMA2_S0_START_ADDR)
#define bfin_read_MDMA2_S0_START_ADDR()   bfin_readPTR(MDMA2_S0_START_ADDR)
#define bfin_write_MDMA2_S0_START_ADDR(val)   bfin_writePTR(MDMA2_S0_START_ADDR, val)
#define pMDMA2_S0_X_COUNT   ((uint16_t volatile *)MDMA2_S0_X_COUNT)
#define bfin_read_MDMA2_S0_X_COUNT()   bfin_read16(MDMA2_S0_X_COUNT)
#define bfin_write_MDMA2_S0_X_COUNT(val)   bfin_write16(MDMA2_S0_X_COUNT, val)
#define pMDMA2_S0_Y_COUNT   ((uint16_t volatile *)MDMA2_S0_Y_COUNT)
#define bfin_read_MDMA2_S0_Y_COUNT()   bfin_read16(MDMA2_S0_Y_COUNT)
#define bfin_write_MDMA2_S0_Y_COUNT(val)   bfin_write16(MDMA2_S0_Y_COUNT, val)
#define pMDMA2_S0_X_MODIFY   ((uint16_t volatile *)MDMA2_S0_X_MODIFY)
#define bfin_read_MDMA2_S0_X_MODIFY()   bfin_read16(MDMA2_S0_X_MODIFY)
#define bfin_write_MDMA2_S0_X_MODIFY(val)   bfin_write16(MDMA2_S0_X_MODIFY, val)
#define pMDMA2_S0_Y_MODIFY   ((uint16_t volatile *)MDMA2_S0_Y_MODIFY)
#define bfin_read_MDMA2_S0_Y_MODIFY()   bfin_read16(MDMA2_S0_Y_MODIFY)
#define bfin_write_MDMA2_S0_Y_MODIFY(val)   bfin_write16(MDMA2_S0_Y_MODIFY, val)
#define pMDMA2_S0_CURR_DESC_PTR   ((void * volatile *)MDMA2_S0_CURR_DESC_PTR)
#define bfin_read_MDMA2_S0_CURR_DESC_PTR()   bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)
#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val)   bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
#define pMDMA2_S0_CURR_ADDR   ((void * volatile *)MDMA2_S0_CURR_ADDR)
#define bfin_read_MDMA2_S0_CURR_ADDR()   bfin_readPTR(MDMA2_S0_CURR_ADDR)
#define bfin_write_MDMA2_S0_CURR_ADDR(val)   bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
#define pMDMA2_S0_CURR_X_COUNT   ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT)
#define bfin_read_MDMA2_S0_CURR_X_COUNT()   bfin_read16(MDMA2_S0_CURR_X_COUNT)
#define bfin_write_MDMA2_S0_CURR_X_COUNT(val)   bfin_write16(MDMA2_S0_CURR_X_COUNT, val)
#define pMDMA2_S0_CURR_Y_COUNT   ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT)
#define bfin_read_MDMA2_S0_CURR_Y_COUNT()   bfin_read16(MDMA2_S0_CURR_Y_COUNT)
#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val)   bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)
#define pMDMA2_S0_IRQ_STATUS   ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS)
#define bfin_read_MDMA2_S0_IRQ_STATUS()   bfin_read16(MDMA2_S0_IRQ_STATUS)
#define bfin_write_MDMA2_S0_IRQ_STATUS(val)   bfin_write16(MDMA2_S0_IRQ_STATUS, val)
#define pMDMA2_S0_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP)
#define bfin_read_MDMA2_S0_PERIPHERAL_MAP()   bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val)   bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)
#define pMDMA2_D0_CONFIG   ((uint16_t volatile *)MDMA2_D0_CONFIG)
#define bfin_read_MDMA2_D0_CONFIG()   bfin_read16(MDMA2_D0_CONFIG)
#define bfin_write_MDMA2_D0_CONFIG(val)   bfin_write16(MDMA2_D0_CONFIG, val)
#define pMDMA2_D0_NEXT_DESC_PTR   ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR)
#define bfin_read_MDMA2_D0_NEXT_DESC_PTR()   bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val)   bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
#define pMDMA2_D0_START_ADDR   ((void * volatile *)MDMA2_D0_START_ADDR)
#define bfin_read_MDMA2_D0_START_ADDR()   bfin_readPTR(MDMA2_D0_START_ADDR)
#define bfin_write_MDMA2_D0_START_ADDR(val)   bfin_writePTR(MDMA2_D0_START_ADDR, val)
#define pMDMA2_D0_X_COUNT   ((uint16_t volatile *)MDMA2_D0_X_COUNT)
#define bfin_read_MDMA2_D0_X_COUNT()   bfin_read16(MDMA2_D0_X_COUNT)
#define bfin_write_MDMA2_D0_X_COUNT(val)   bfin_write16(MDMA2_D0_X_COUNT, val)
#define pMDMA2_D0_Y_COUNT   ((uint16_t volatile *)MDMA2_D0_Y_COUNT)
#define bfin_read_MDMA2_D0_Y_COUNT()   bfin_read16(MDMA2_D0_Y_COUNT)
#define bfin_write_MDMA2_D0_Y_COUNT(val)   bfin_write16(MDMA2_D0_Y_COUNT, val)
#define pMDMA2_D0_X_MODIFY   ((uint16_t volatile *)MDMA2_D0_X_MODIFY)
#define bfin_read_MDMA2_D0_X_MODIFY()   bfin_read16(MDMA2_D0_X_MODIFY)
#define bfin_write_MDMA2_D0_X_MODIFY(val)   bfin_write16(MDMA2_D0_X_MODIFY, val)
#define pMDMA2_D0_Y_MODIFY   ((uint16_t volatile *)MDMA2_D0_Y_MODIFY)
#define bfin_read_MDMA2_D0_Y_MODIFY()   bfin_read16(MDMA2_D0_Y_MODIFY)
#define bfin_write_MDMA2_D0_Y_MODIFY(val)   bfin_write16(MDMA2_D0_Y_MODIFY, val)
#define pMDMA2_D0_CURR_DESC_PTR   ((void * volatile *)MDMA2_D0_CURR_DESC_PTR)
#define bfin_read_MDMA2_D0_CURR_DESC_PTR()   bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)
#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val)   bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
#define pMDMA2_D0_CURR_ADDR   ((void * volatile *)MDMA2_D0_CURR_ADDR)
#define bfin_read_MDMA2_D0_CURR_ADDR()   bfin_readPTR(MDMA2_D0_CURR_ADDR)
#define bfin_write_MDMA2_D0_CURR_ADDR(val)   bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
#define pMDMA2_D0_CURR_X_COUNT   ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT)
#define bfin_read_MDMA2_D0_CURR_X_COUNT()   bfin_read16(MDMA2_D0_CURR_X_COUNT)
#define bfin_write_MDMA2_D0_CURR_X_COUNT(val)   bfin_write16(MDMA2_D0_CURR_X_COUNT, val)
#define pMDMA2_D0_CURR_Y_COUNT   ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT)
#define bfin_read_MDMA2_D0_CURR_Y_COUNT()   bfin_read16(MDMA2_D0_CURR_Y_COUNT)
#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val)   bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)
#define pMDMA2_D0_IRQ_STATUS   ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS)
#define bfin_read_MDMA2_D0_IRQ_STATUS()   bfin_read16(MDMA2_D0_IRQ_STATUS)
#define bfin_write_MDMA2_D0_IRQ_STATUS(val)   bfin_write16(MDMA2_D0_IRQ_STATUS, val)
#define pMDMA2_D0_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP)
#define bfin_read_MDMA2_D0_PERIPHERAL_MAP()   bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val)   bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)
#define pMDMA2_S1_CONFIG   ((uint16_t volatile *)MDMA2_S1_CONFIG)
#define bfin_read_MDMA2_S1_CONFIG()   bfin_read16(MDMA2_S1_CONFIG)
#define bfin_write_MDMA2_S1_CONFIG(val)   bfin_write16(MDMA2_S1_CONFIG, val)
#define pMDMA2_S1_NEXT_DESC_PTR   ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR)
#define bfin_read_MDMA2_S1_NEXT_DESC_PTR()   bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val)   bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
#define pMDMA2_S1_START_ADDR   ((void * volatile *)MDMA2_S1_START_ADDR)
#define bfin_read_MDMA2_S1_START_ADDR()   bfin_readPTR(MDMA2_S1_START_ADDR)
#define bfin_write_MDMA2_S1_START_ADDR(val)   bfin_writePTR(MDMA2_S1_START_ADDR, val)
#define pMDMA2_S1_X_COUNT   ((uint16_t volatile *)MDMA2_S1_X_COUNT)
#define bfin_read_MDMA2_S1_X_COUNT()   bfin_read16(MDMA2_S1_X_COUNT)
#define bfin_write_MDMA2_S1_X_COUNT(val)   bfin_write16(MDMA2_S1_X_COUNT, val)
#define pMDMA2_S1_Y_COUNT   ((uint16_t volatile *)MDMA2_S1_Y_COUNT)
#define bfin_read_MDMA2_S1_Y_COUNT()   bfin_read16(MDMA2_S1_Y_COUNT)
#define bfin_write_MDMA2_S1_Y_COUNT(val)   bfin_write16(MDMA2_S1_Y_COUNT, val)
#define pMDMA2_S1_X_MODIFY   ((uint16_t volatile *)MDMA2_S1_X_MODIFY)
#define bfin_read_MDMA2_S1_X_MODIFY()   bfin_read16(MDMA2_S1_X_MODIFY)
#define bfin_write_MDMA2_S1_X_MODIFY(val)   bfin_write16(MDMA2_S1_X_MODIFY, val)
#define pMDMA2_S1_Y_MODIFY   ((uint16_t volatile *)MDMA2_S1_Y_MODIFY)
#define bfin_read_MDMA2_S1_Y_MODIFY()   bfin_read16(MDMA2_S1_Y_MODIFY)
#define bfin_write_MDMA2_S1_Y_MODIFY(val)   bfin_write16(MDMA2_S1_Y_MODIFY, val)
#define pMDMA2_S1_CURR_DESC_PTR   ((void * volatile *)MDMA2_S1_CURR_DESC_PTR)
#define bfin_read_MDMA2_S1_CURR_DESC_PTR()   bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)
#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val)   bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
#define pMDMA2_S1_CURR_ADDR   ((void * volatile *)MDMA2_S1_CURR_ADDR)
#define bfin_read_MDMA2_S1_CURR_ADDR()   bfin_readPTR(MDMA2_S1_CURR_ADDR)
#define bfin_write_MDMA2_S1_CURR_ADDR(val)   bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
#define pMDMA2_S1_CURR_X_COUNT   ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT)
#define bfin_read_MDMA2_S1_CURR_X_COUNT()   bfin_read16(MDMA2_S1_CURR_X_COUNT)
#define bfin_write_MDMA2_S1_CURR_X_COUNT(val)   bfin_write16(MDMA2_S1_CURR_X_COUNT, val)
#define pMDMA2_S1_CURR_Y_COUNT   ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT)
#define bfin_read_MDMA2_S1_CURR_Y_COUNT()   bfin_read16(MDMA2_S1_CURR_Y_COUNT)
#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val)   bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)
#define pMDMA2_S1_IRQ_STATUS   ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS)
#define bfin_read_MDMA2_S1_IRQ_STATUS()   bfin_read16(MDMA2_S1_IRQ_STATUS)
#define bfin_write_MDMA2_S1_IRQ_STATUS(val)   bfin_write16(MDMA2_S1_IRQ_STATUS, val)
#define pMDMA2_S1_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP)
#define bfin_read_MDMA2_S1_PERIPHERAL_MAP()   bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val)   bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)
#define pMDMA2_D1_CONFIG   ((uint16_t volatile *)MDMA2_D1_CONFIG)
#define bfin_read_MDMA2_D1_CONFIG()   bfin_read16(MDMA2_D1_CONFIG)
#define bfin_write_MDMA2_D1_CONFIG(val)   bfin_write16(MDMA2_D1_CONFIG, val)
#define pMDMA2_D1_NEXT_DESC_PTR   ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR)
#define bfin_read_MDMA2_D1_NEXT_DESC_PTR()   bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val)   bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
#define pMDMA2_D1_START_ADDR   ((void * volatile *)MDMA2_D1_START_ADDR)
#define bfin_read_MDMA2_D1_START_ADDR()   bfin_readPTR(MDMA2_D1_START_ADDR)
#define bfin_write_MDMA2_D1_START_ADDR(val)   bfin_writePTR(MDMA2_D1_START_ADDR, val)
#define pMDMA2_D1_X_COUNT   ((uint16_t volatile *)MDMA2_D1_X_COUNT)
#define bfin_read_MDMA2_D1_X_COUNT()   bfin_read16(MDMA2_D1_X_COUNT)
#define bfin_write_MDMA2_D1_X_COUNT(val)   bfin_write16(MDMA2_D1_X_COUNT, val)
#define pMDMA2_D1_Y_COUNT   ((uint16_t volatile *)MDMA2_D1_Y_COUNT)
#define bfin_read_MDMA2_D1_Y_COUNT()   bfin_read16(MDMA2_D1_Y_COUNT)
#define bfin_write_MDMA2_D1_Y_COUNT(val)   bfin_write16(MDMA2_D1_Y_COUNT, val)
#define pMDMA2_D1_X_MODIFY   ((uint16_t volatile *)MDMA2_D1_X_MODIFY)
#define bfin_read_MDMA2_D1_X_MODIFY()   bfin_read16(MDMA2_D1_X_MODIFY)
#define bfin_write_MDMA2_D1_X_MODIFY(val)   bfin_write16(MDMA2_D1_X_MODIFY, val)
#define pMDMA2_D1_Y_MODIFY   ((uint16_t volatile *)MDMA2_D1_Y_MODIFY)
#define bfin_read_MDMA2_D1_Y_MODIFY()   bfin_read16(MDMA2_D1_Y_MODIFY)
#define bfin_write_MDMA2_D1_Y_MODIFY(val)   bfin_write16(MDMA2_D1_Y_MODIFY, val)
#define pMDMA2_D1_CURR_DESC_PTR   ((void * volatile *)MDMA2_D1_CURR_DESC_PTR)
#define bfin_read_MDMA2_D1_CURR_DESC_PTR()   bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)
#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val)   bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
#define pMDMA2_D1_CURR_ADDR   ((void * volatile *)MDMA2_D1_CURR_ADDR)
#define bfin_read_MDMA2_D1_CURR_ADDR()   bfin_readPTR(MDMA2_D1_CURR_ADDR)
#define bfin_write_MDMA2_D1_CURR_ADDR(val)   bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
#define pMDMA2_D1_CURR_X_COUNT   ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT)
#define bfin_read_MDMA2_D1_CURR_X_COUNT()   bfin_read16(MDMA2_D1_CURR_X_COUNT)
#define bfin_write_MDMA2_D1_CURR_X_COUNT(val)   bfin_write16(MDMA2_D1_CURR_X_COUNT, val)
#define pMDMA2_D1_CURR_Y_COUNT   ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT)
#define bfin_read_MDMA2_D1_CURR_Y_COUNT()   bfin_read16(MDMA2_D1_CURR_Y_COUNT)
#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val)   bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)
#define pMDMA2_D1_IRQ_STATUS   ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS)
#define bfin_read_MDMA2_D1_IRQ_STATUS()   bfin_read16(MDMA2_D1_IRQ_STATUS)
#define bfin_write_MDMA2_D1_IRQ_STATUS(val)   bfin_write16(MDMA2_D1_IRQ_STATUS, val)
#define pMDMA2_D1_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP)
#define bfin_read_MDMA2_D1_PERIPHERAL_MAP()   bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val)   bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)
#define pTIMER0_CONFIG   ((uint16_t volatile *)TIMER0_CONFIG)
#define bfin_read_TIMER0_CONFIG()   bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val)   bfin_write16(TIMER0_CONFIG, val)
#define pTIMER0_COUNTER   ((uint32_t volatile *)TIMER0_COUNTER)
#define bfin_read_TIMER0_COUNTER()   bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val)   bfin_write32(TIMER0_COUNTER, val)
#define pTIMER0_PERIOD   ((uint32_t volatile *)TIMER0_PERIOD)
#define bfin_read_TIMER0_PERIOD()   bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val)   bfin_write32(TIMER0_PERIOD, val)
#define pTIMER0_WIDTH   ((uint32_t volatile *)TIMER0_WIDTH)
#define bfin_read_TIMER0_WIDTH()   bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
#define pTIMER1_CONFIG   ((uint16_t volatile *)TIMER1_CONFIG)
#define bfin_read_TIMER1_CONFIG()   bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val)   bfin_write16(TIMER1_CONFIG, val)
#define pTIMER1_COUNTER   ((uint32_t volatile *)TIMER1_COUNTER)
#define bfin_read_TIMER1_COUNTER()   bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val)   bfin_write32(TIMER1_COUNTER, val)
#define pTIMER1_PERIOD   ((uint32_t volatile *)TIMER1_PERIOD)
#define bfin_read_TIMER1_PERIOD()   bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val)   bfin_write32(TIMER1_PERIOD, val)
#define pTIMER1_WIDTH   ((uint32_t volatile *)TIMER1_WIDTH)
#define bfin_read_TIMER1_WIDTH()   bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
#define pTIMER2_CONFIG   ((uint16_t volatile *)TIMER2_CONFIG)
#define bfin_read_TIMER2_CONFIG()   bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val)   bfin_write16(TIMER2_CONFIG, val)
#define pTIMER2_COUNTER   ((uint32_t volatile *)TIMER2_COUNTER)
#define bfin_read_TIMER2_COUNTER()   bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val)   bfin_write32(TIMER2_COUNTER, val)
#define pTIMER2_PERIOD   ((uint32_t volatile *)TIMER2_PERIOD)
#define bfin_read_TIMER2_PERIOD()   bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val)   bfin_write32(TIMER2_PERIOD, val)
#define pTIMER2_WIDTH   ((uint32_t volatile *)TIMER2_WIDTH)
#define bfin_read_TIMER2_WIDTH()   bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
#define pTIMER3_CONFIG   ((uint16_t volatile *)TIMER3_CONFIG)
#define bfin_read_TIMER3_CONFIG()   bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val)   bfin_write16(TIMER3_CONFIG, val)
#define pTIMER3_COUNTER   ((uint32_t volatile *)TIMER3_COUNTER)
#define bfin_read_TIMER3_COUNTER()   bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val)   bfin_write32(TIMER3_COUNTER, val)
#define pTIMER3_PERIOD   ((uint32_t volatile *)TIMER3_PERIOD)
#define bfin_read_TIMER3_PERIOD()   bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val)   bfin_write32(TIMER3_PERIOD, val)
#define pTIMER3_WIDTH   ((uint32_t volatile *)TIMER3_WIDTH)
#define bfin_read_TIMER3_WIDTH()   bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
#define pTIMER4_CONFIG   ((uint16_t volatile *)TIMER4_CONFIG)
#define bfin_read_TIMER4_CONFIG()   bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val)   bfin_write16(TIMER4_CONFIG, val)
#define pTIMER4_COUNTER   ((uint32_t volatile *)TIMER4_COUNTER)
#define bfin_read_TIMER4_COUNTER()   bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val)   bfin_write32(TIMER4_COUNTER, val)
#define pTIMER4_PERIOD   ((uint32_t volatile *)TIMER4_PERIOD)
#define bfin_read_TIMER4_PERIOD()   bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val)   bfin_write32(TIMER4_PERIOD, val)
#define pTIMER4_WIDTH   ((uint32_t volatile *)TIMER4_WIDTH)
#define bfin_read_TIMER4_WIDTH()   bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
#define pTIMER5_CONFIG   ((uint16_t volatile *)TIMER5_CONFIG)
#define bfin_read_TIMER5_CONFIG()   bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val)   bfin_write16(TIMER5_CONFIG, val)
#define pTIMER5_COUNTER   ((uint32_t volatile *)TIMER5_COUNTER)
#define bfin_read_TIMER5_COUNTER()   bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val)   bfin_write32(TIMER5_COUNTER, val)
#define pTIMER5_PERIOD   ((uint32_t volatile *)TIMER5_PERIOD)
#define bfin_read_TIMER5_PERIOD()   bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val)   bfin_write32(TIMER5_PERIOD, val)
#define pTIMER5_WIDTH   ((uint32_t volatile *)TIMER5_WIDTH)
#define bfin_read_TIMER5_WIDTH()   bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
#define pTIMER6_CONFIG   ((uint16_t volatile *)TIMER6_CONFIG)
#define bfin_read_TIMER6_CONFIG()   bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val)   bfin_write16(TIMER6_CONFIG, val)
#define pTIMER6_COUNTER   ((uint32_t volatile *)TIMER6_COUNTER)
#define bfin_read_TIMER6_COUNTER()   bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val)   bfin_write32(TIMER6_COUNTER, val)
#define pTIMER6_PERIOD   ((uint32_t volatile *)TIMER6_PERIOD)
#define bfin_read_TIMER6_PERIOD()   bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val)   bfin_write32(TIMER6_PERIOD, val)
#define pTIMER6_WIDTH   ((uint32_t volatile *)TIMER6_WIDTH)
#define bfin_read_TIMER6_WIDTH()   bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
#define pTIMER7_CONFIG   ((uint16_t volatile *)TIMER7_CONFIG)
#define bfin_read_TIMER7_CONFIG()   bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val)   bfin_write16(TIMER7_CONFIG, val)
#define pTIMER7_COUNTER   ((uint32_t volatile *)TIMER7_COUNTER)
#define bfin_read_TIMER7_COUNTER()   bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val)   bfin_write32(TIMER7_COUNTER, val)
#define pTIMER7_PERIOD   ((uint32_t volatile *)TIMER7_PERIOD)
#define bfin_read_TIMER7_PERIOD()   bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val)   bfin_write32(TIMER7_PERIOD, val)
#define pTIMER7_WIDTH   ((uint32_t volatile *)TIMER7_WIDTH)
#define bfin_read_TIMER7_WIDTH()   bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
#define pTIMER8_CONFIG   ((uint16_t volatile *)TIMER8_CONFIG)
#define bfin_read_TIMER8_CONFIG()   bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val)   bfin_write16(TIMER8_CONFIG, val)
#define pTIMER8_COUNTER   ((uint32_t volatile *)TIMER8_COUNTER)
#define bfin_read_TIMER8_COUNTER()   bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val)   bfin_write32(TIMER8_COUNTER, val)
#define pTIMER8_PERIOD   ((uint32_t volatile *)TIMER8_PERIOD)
#define bfin_read_TIMER8_PERIOD()   bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val)   bfin_write32(TIMER8_PERIOD, val)
#define pTIMER8_WIDTH   ((uint32_t volatile *)TIMER8_WIDTH)
#define bfin_read_TIMER8_WIDTH()   bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
#define pTIMER9_CONFIG   ((uint16_t volatile *)TIMER9_CONFIG)
#define bfin_read_TIMER9_CONFIG()   bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val)   bfin_write16(TIMER9_CONFIG, val)
#define pTIMER9_COUNTER   ((uint32_t volatile *)TIMER9_COUNTER)
#define bfin_read_TIMER9_COUNTER()   bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val)   bfin_write32(TIMER9_COUNTER, val)
#define pTIMER9_PERIOD   ((uint32_t volatile *)TIMER9_PERIOD)
#define bfin_read_TIMER9_PERIOD()   bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val)   bfin_write32(TIMER9_PERIOD, val)
#define pTIMER9_WIDTH   ((uint32_t volatile *)TIMER9_WIDTH)
#define bfin_read_TIMER9_WIDTH()   bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
#define pTIMER10_CONFIG   ((uint16_t volatile *)TIMER10_CONFIG)
#define bfin_read_TIMER10_CONFIG()   bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val)   bfin_write16(TIMER10_CONFIG, val)
#define pTIMER10_COUNTER   ((uint32_t volatile *)TIMER10_COUNTER)
#define bfin_read_TIMER10_COUNTER()   bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val)   bfin_write32(TIMER10_COUNTER, val)
#define pTIMER10_PERIOD   ((uint32_t volatile *)TIMER10_PERIOD)
#define bfin_read_TIMER10_PERIOD()   bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val)   bfin_write32(TIMER10_PERIOD, val)
#define pTIMER10_WIDTH   ((uint32_t volatile *)TIMER10_WIDTH)
#define bfin_read_TIMER10_WIDTH()   bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val)   bfin_write32(TIMER10_WIDTH, val)
#define pTIMER11_CONFIG   ((uint16_t volatile *)TIMER11_CONFIG)
#define bfin_read_TIMER11_CONFIG()   bfin_read16(TIMER11_CONFIG)
#define bfin_write_TIMER11_CONFIG(val)   bfin_write16(TIMER11_CONFIG, val)
#define pTIMER11_COUNTER   ((uint32_t volatile *)TIMER11_COUNTER)
#define bfin_read_TIMER11_COUNTER()   bfin_read32(TIMER11_COUNTER)
#define bfin_write_TIMER11_COUNTER(val)   bfin_write32(TIMER11_COUNTER, val)
#define pTIMER11_PERIOD   ((uint32_t volatile *)TIMER11_PERIOD)
#define bfin_read_TIMER11_PERIOD()   bfin_read32(TIMER11_PERIOD)
#define bfin_write_TIMER11_PERIOD(val)   bfin_write32(TIMER11_PERIOD, val)
#define pTIMER11_WIDTH   ((uint32_t volatile *)TIMER11_WIDTH)
#define bfin_read_TIMER11_WIDTH()   bfin_read32(TIMER11_WIDTH)
#define bfin_write_TIMER11_WIDTH(val)   bfin_write32(TIMER11_WIDTH, val)
#define pTMRS4_ENABLE   ((uint32_t volatile *)TMRS4_ENABLE)
#define bfin_read_TMRS4_ENABLE()   bfin_read32(TMRS4_ENABLE)
#define bfin_write_TMRS4_ENABLE(val)   bfin_write32(TMRS4_ENABLE, val)
#define pTMRS4_DISABLE   ((uint32_t volatile *)TMRS4_DISABLE)
#define bfin_read_TMRS4_DISABLE()   bfin_read32(TMRS4_DISABLE)
#define bfin_write_TMRS4_DISABLE(val)   bfin_write32(TMRS4_DISABLE, val)
#define pTMRS4_STATUS   ((uint32_t volatile *)TMRS4_STATUS)
#define bfin_read_TMRS4_STATUS()   bfin_read32(TMRS4_STATUS)
#define bfin_write_TMRS4_STATUS(val)   bfin_write32(TMRS4_STATUS, val)
#define pTMRS8_ENABLE   ((uint32_t volatile *)TMRS8_ENABLE)
#define bfin_read_TMRS8_ENABLE()   bfin_read32(TMRS8_ENABLE)
#define bfin_write_TMRS8_ENABLE(val)   bfin_write32(TMRS8_ENABLE, val)
#define pTMRS8_DISABLE   ((uint32_t volatile *)TMRS8_DISABLE)
#define bfin_read_TMRS8_DISABLE()   bfin_read32(TMRS8_DISABLE)
#define bfin_write_TMRS8_DISABLE(val)   bfin_write32(TMRS8_DISABLE, val)
#define pTMRS8_STATUS   ((uint32_t volatile *)TMRS8_STATUS)
#define bfin_read_TMRS8_STATUS()   bfin_read32(TMRS8_STATUS)
#define bfin_write_TMRS8_STATUS(val)   bfin_write32(TMRS8_STATUS, val)
#define pFIO0_FLAG_D   ((uint16_t volatile *)FIO0_FLAG_D)
#define bfin_read_FIO0_FLAG_D()   bfin_read16(FIO0_FLAG_D)
#define bfin_write_FIO0_FLAG_D(val)   bfin_write16(FIO0_FLAG_D, val)
#define pFIO0_FLAG_C   ((uint16_t volatile *)FIO0_FLAG_C)
#define bfin_read_FIO0_FLAG_C()   bfin_read16(FIO0_FLAG_C)
#define bfin_write_FIO0_FLAG_C(val)   bfin_write16(FIO0_FLAG_C, val)
#define pFIO0_FLAG_S   ((uint16_t volatile *)FIO0_FLAG_S)
#define bfin_read_FIO0_FLAG_S()   bfin_read16(FIO0_FLAG_S)
#define bfin_write_FIO0_FLAG_S(val)   bfin_write16(FIO0_FLAG_S, val)
#define pFIO0_FLAG_T   ((uint16_t volatile *)FIO0_FLAG_T)
#define bfin_read_FIO0_FLAG_T()   bfin_read16(FIO0_FLAG_T)
#define bfin_write_FIO0_FLAG_T(val)   bfin_write16(FIO0_FLAG_T, val)
#define pFIO0_MASKA_D   ((uint16_t volatile *)FIO0_MASKA_D)
#define bfin_read_FIO0_MASKA_D()   bfin_read16(FIO0_MASKA_D)
#define bfin_write_FIO0_MASKA_D(val)   bfin_write16(FIO0_MASKA_D, val)
#define pFIO0_MASKA_C   ((uint16_t volatile *)FIO0_MASKA_C)
#define bfin_read_FIO0_MASKA_C()   bfin_read16(FIO0_MASKA_C)
#define bfin_write_FIO0_MASKA_C(val)   bfin_write16(FIO0_MASKA_C, val)
#define pFIO0_MASKA_S   ((uint16_t volatile *)FIO0_MASKA_S)
#define bfin_read_FIO0_MASKA_S()   bfin_read16(FIO0_MASKA_S)
#define bfin_write_FIO0_MASKA_S(val)   bfin_write16(FIO0_MASKA_S, val)
#define pFIO0_MASKA_T   ((uint16_t volatile *)FIO0_MASKA_T)
#define bfin_read_FIO0_MASKA_T()   bfin_read16(FIO0_MASKA_T)
#define bfin_write_FIO0_MASKA_T(val)   bfin_write16(FIO0_MASKA_T, val)
#define pFIO0_MASKB_D   ((uint16_t volatile *)FIO0_MASKB_D)
#define bfin_read_FIO0_MASKB_D()   bfin_read16(FIO0_MASKB_D)
#define bfin_write_FIO0_MASKB_D(val)   bfin_write16(FIO0_MASKB_D, val)
#define pFIO0_MASKB_C   ((uint16_t volatile *)FIO0_MASKB_C)
#define bfin_read_FIO0_MASKB_C()   bfin_read16(FIO0_MASKB_C)
#define bfin_write_FIO0_MASKB_C(val)   bfin_write16(FIO0_MASKB_C, val)
#define pFIO0_MASKB_S   ((uint16_t volatile *)FIO0_MASKB_S)
#define bfin_read_FIO0_MASKB_S()   bfin_read16(FIO0_MASKB_S)
#define bfin_write_FIO0_MASKB_S(val)   bfin_write16(FIO0_MASKB_S, val)
#define pFIO0_MASKB_T   ((uint16_t volatile *)FIO0_MASKB_T)
#define bfin_read_FIO0_MASKB_T()   bfin_read16(FIO0_MASKB_T)
#define bfin_write_FIO0_MASKB_T(val)   bfin_write16(FIO0_MASKB_T, val)
#define pFIO0_DIR   ((uint16_t volatile *)FIO0_DIR)
#define bfin_read_FIO0_DIR()   bfin_read16(FIO0_DIR)
#define bfin_write_FIO0_DIR(val)   bfin_write16(FIO0_DIR, val)
#define pFIO0_POLAR   ((uint16_t volatile *)FIO0_POLAR)
#define bfin_read_FIO0_POLAR()   bfin_read16(FIO0_POLAR)
#define bfin_write_FIO0_POLAR(val)   bfin_write16(FIO0_POLAR, val)
#define pFIO0_EDGE   ((uint16_t volatile *)FIO0_EDGE)
#define bfin_read_FIO0_EDGE()   bfin_read16(FIO0_EDGE)
#define bfin_write_FIO0_EDGE(val)   bfin_write16(FIO0_EDGE, val)
#define pFIO0_BOTH   ((uint16_t volatile *)FIO0_BOTH)
#define bfin_read_FIO0_BOTH()   bfin_read16(FIO0_BOTH)
#define bfin_write_FIO0_BOTH(val)   bfin_write16(FIO0_BOTH, val)
#define pFIO0_INEN   ((uint16_t volatile *)FIO0_INEN)
#define bfin_read_FIO0_INEN()   bfin_read16(FIO0_INEN)
#define bfin_write_FIO0_INEN(val)   bfin_write16(FIO0_INEN, val)
#define pFIO1_FLAG_D   ((uint16_t volatile *)FIO1_FLAG_D)
#define bfin_read_FIO1_FLAG_D()   bfin_read16(FIO1_FLAG_D)
#define bfin_write_FIO1_FLAG_D(val)   bfin_write16(FIO1_FLAG_D, val)
#define pFIO1_FLAG_C   ((uint16_t volatile *)FIO1_FLAG_C)
#define bfin_read_FIO1_FLAG_C()   bfin_read16(FIO1_FLAG_C)
#define bfin_write_FIO1_FLAG_C(val)   bfin_write16(FIO1_FLAG_C, val)
#define pFIO1_FLAG_S   ((uint16_t volatile *)FIO1_FLAG_S)
#define bfin_read_FIO1_FLAG_S()   bfin_read16(FIO1_FLAG_S)
#define bfin_write_FIO1_FLAG_S(val)   bfin_write16(FIO1_FLAG_S, val)
#define pFIO1_FLAG_T   ((uint16_t volatile *)FIO1_FLAG_T)
#define bfin_read_FIO1_FLAG_T()   bfin_read16(FIO1_FLAG_T)
#define bfin_write_FIO1_FLAG_T(val)   bfin_write16(FIO1_FLAG_T, val)
#define pFIO1_MASKA_D   ((uint16_t volatile *)FIO1_MASKA_D)
#define bfin_read_FIO1_MASKA_D()   bfin_read16(FIO1_MASKA_D)
#define bfin_write_FIO1_MASKA_D(val)   bfin_write16(FIO1_MASKA_D, val)
#define pFIO1_MASKA_C   ((uint16_t volatile *)FIO1_MASKA_C)
#define bfin_read_FIO1_MASKA_C()   bfin_read16(FIO1_MASKA_C)
#define bfin_write_FIO1_MASKA_C(val)   bfin_write16(FIO1_MASKA_C, val)
#define pFIO1_MASKA_S   ((uint16_t volatile *)FIO1_MASKA_S)
#define bfin_read_FIO1_MASKA_S()   bfin_read16(FIO1_MASKA_S)
#define bfin_write_FIO1_MASKA_S(val)   bfin_write16(FIO1_MASKA_S, val)
#define pFIO1_MASKA_T   ((uint16_t volatile *)FIO1_MASKA_T)
#define bfin_read_FIO1_MASKA_T()   bfin_read16(FIO1_MASKA_T)
#define bfin_write_FIO1_MASKA_T(val)   bfin_write16(FIO1_MASKA_T, val)
#define pFIO1_MASKB_D   ((uint16_t volatile *)FIO1_MASKB_D)
#define bfin_read_FIO1_MASKB_D()   bfin_read16(FIO1_MASKB_D)
#define bfin_write_FIO1_MASKB_D(val)   bfin_write16(FIO1_MASKB_D, val)
#define pFIO1_MASKB_C   ((uint16_t volatile *)FIO1_MASKB_C)
#define bfin_read_FIO1_MASKB_C()   bfin_read16(FIO1_MASKB_C)
#define bfin_write_FIO1_MASKB_C(val)   bfin_write16(FIO1_MASKB_C, val)
#define pFIO1_MASKB_S   ((uint16_t volatile *)FIO1_MASKB_S)
#define bfin_read_FIO1_MASKB_S()   bfin_read16(FIO1_MASKB_S)
#define bfin_write_FIO1_MASKB_S(val)   bfin_write16(FIO1_MASKB_S, val)
#define pFIO1_MASKB_T   ((uint16_t volatile *)FIO1_MASKB_T)
#define bfin_read_FIO1_MASKB_T()   bfin_read16(FIO1_MASKB_T)
#define bfin_write_FIO1_MASKB_T(val)   bfin_write16(FIO1_MASKB_T, val)
#define pFIO1_DIR   ((uint16_t volatile *)FIO1_DIR)
#define bfin_read_FIO1_DIR()   bfin_read16(FIO1_DIR)
#define bfin_write_FIO1_DIR(val)   bfin_write16(FIO1_DIR, val)
#define pFIO1_POLAR   ((uint16_t volatile *)FIO1_POLAR)
#define bfin_read_FIO1_POLAR()   bfin_read16(FIO1_POLAR)
#define bfin_write_FIO1_POLAR(val)   bfin_write16(FIO1_POLAR, val)
#define pFIO1_EDGE   ((uint16_t volatile *)FIO1_EDGE)
#define bfin_read_FIO1_EDGE()   bfin_read16(FIO1_EDGE)
#define bfin_write_FIO1_EDGE(val)   bfin_write16(FIO1_EDGE, val)
#define pFIO1_BOTH   ((uint16_t volatile *)FIO1_BOTH)
#define bfin_read_FIO1_BOTH()   bfin_read16(FIO1_BOTH)
#define bfin_write_FIO1_BOTH(val)   bfin_write16(FIO1_BOTH, val)
#define pFIO1_INEN   ((uint16_t volatile *)FIO1_INEN)
#define bfin_read_FIO1_INEN()   bfin_read16(FIO1_INEN)
#define bfin_write_FIO1_INEN(val)   bfin_write16(FIO1_INEN, val)
#define pFIO2_FLAG_D   ((uint16_t volatile *)FIO2_FLAG_D)
#define bfin_read_FIO2_FLAG_D()   bfin_read16(FIO2_FLAG_D)
#define bfin_write_FIO2_FLAG_D(val)   bfin_write16(FIO2_FLAG_D, val)
#define pFIO2_FLAG_C   ((uint16_t volatile *)FIO2_FLAG_C)
#define bfin_read_FIO2_FLAG_C()   bfin_read16(FIO2_FLAG_C)
#define bfin_write_FIO2_FLAG_C(val)   bfin_write16(FIO2_FLAG_C, val)
#define pFIO2_FLAG_S   ((uint16_t volatile *)FIO2_FLAG_S)
#define bfin_read_FIO2_FLAG_S()   bfin_read16(FIO2_FLAG_S)
#define bfin_write_FIO2_FLAG_S(val)   bfin_write16(FIO2_FLAG_S, val)
#define pFIO2_FLAG_T   ((uint16_t volatile *)FIO2_FLAG_T)
#define bfin_read_FIO2_FLAG_T()   bfin_read16(FIO2_FLAG_T)
#define bfin_write_FIO2_FLAG_T(val)   bfin_write16(FIO2_FLAG_T, val)
#define pFIO2_MASKA_D   ((uint16_t volatile *)FIO2_MASKA_D)
#define bfin_read_FIO2_MASKA_D()   bfin_read16(FIO2_MASKA_D)
#define bfin_write_FIO2_MASKA_D(val)   bfin_write16(FIO2_MASKA_D, val)
#define pFIO2_MASKA_C   ((uint16_t volatile *)FIO2_MASKA_C)
#define bfin_read_FIO2_MASKA_C()   bfin_read16(FIO2_MASKA_C)
#define bfin_write_FIO2_MASKA_C(val)   bfin_write16(FIO2_MASKA_C, val)
#define pFIO2_MASKA_S   ((uint16_t volatile *)FIO2_MASKA_S)
#define bfin_read_FIO2_MASKA_S()   bfin_read16(FIO2_MASKA_S)
#define bfin_write_FIO2_MASKA_S(val)   bfin_write16(FIO2_MASKA_S, val)
#define pFIO2_MASKA_T   ((uint16_t volatile *)FIO2_MASKA_T)
#define bfin_read_FIO2_MASKA_T()   bfin_read16(FIO2_MASKA_T)
#define bfin_write_FIO2_MASKA_T(val)   bfin_write16(FIO2_MASKA_T, val)
#define pFIO2_MASKB_D   ((uint16_t volatile *)FIO2_MASKB_D)
#define bfin_read_FIO2_MASKB_D()   bfin_read16(FIO2_MASKB_D)
#define bfin_write_FIO2_MASKB_D(val)   bfin_write16(FIO2_MASKB_D, val)
#define pFIO2_MASKB_C   ((uint16_t volatile *)FIO2_MASKB_C)
#define bfin_read_FIO2_MASKB_C()   bfin_read16(FIO2_MASKB_C)
#define bfin_write_FIO2_MASKB_C(val)   bfin_write16(FIO2_MASKB_C, val)
#define pFIO2_MASKB_S   ((uint16_t volatile *)FIO2_MASKB_S)
#define bfin_read_FIO2_MASKB_S()   bfin_read16(FIO2_MASKB_S)
#define bfin_write_FIO2_MASKB_S(val)   bfin_write16(FIO2_MASKB_S, val)
#define pFIO2_MASKB_T   ((uint16_t volatile *)FIO2_MASKB_T)
#define bfin_read_FIO2_MASKB_T()   bfin_read16(FIO2_MASKB_T)
#define bfin_write_FIO2_MASKB_T(val)   bfin_write16(FIO2_MASKB_T, val)
#define pFIO2_DIR   ((uint16_t volatile *)FIO2_DIR)
#define bfin_read_FIO2_DIR()   bfin_read16(FIO2_DIR)
#define bfin_write_FIO2_DIR(val)   bfin_write16(FIO2_DIR, val)
#define pFIO2_POLAR   ((uint16_t volatile *)FIO2_POLAR)
#define bfin_read_FIO2_POLAR()   bfin_read16(FIO2_POLAR)
#define bfin_write_FIO2_POLAR(val)   bfin_write16(FIO2_POLAR, val)
#define pFIO2_EDGE   ((uint16_t volatile *)FIO2_EDGE)
#define bfin_read_FIO2_EDGE()   bfin_read16(FIO2_EDGE)
#define bfin_write_FIO2_EDGE(val)   bfin_write16(FIO2_EDGE, val)
#define pFIO2_BOTH   ((uint16_t volatile *)FIO2_BOTH)
#define bfin_read_FIO2_BOTH()   bfin_read16(FIO2_BOTH)
#define bfin_write_FIO2_BOTH(val)   bfin_write16(FIO2_BOTH, val)
#define pFIO2_INEN   ((uint16_t volatile *)FIO2_INEN)
#define bfin_read_FIO2_INEN()   bfin_read16(FIO2_INEN)
#define bfin_write_FIO2_INEN(val)   bfin_write16(FIO2_INEN, val)
#define pSPORT0_TCR1   ((uint16_t volatile *)SPORT0_TCR1)
#define bfin_read_SPORT0_TCR1()   bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val)   bfin_write16(SPORT0_TCR1, val)
#define pSPORT0_TCR2   ((uint16_t volatile *)SPORT0_TCR2)
#define bfin_read_SPORT0_TCR2()   bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val)   bfin_write16(SPORT0_TCR2, val)
#define pSPORT0_TCLKDIV   ((uint16_t volatile *)SPORT0_TCLKDIV)
#define bfin_read_SPORT0_TCLKDIV()   bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val)   bfin_write16(SPORT0_TCLKDIV, val)
#define pSPORT0_TFSDIV   ((uint16_t volatile *)SPORT0_TFSDIV)
#define bfin_read_SPORT0_TFSDIV()   bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val)   bfin_write16(SPORT0_TFSDIV, val)
#define pSPORT0_TX   ((uint32_t volatile *)SPORT0_TX)
#define bfin_read_SPORT0_TX()   bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val)   bfin_write32(SPORT0_TX, val)
#define pSPORT0_RX   ((uint32_t volatile *)SPORT0_RX)
#define bfin_read_SPORT0_RX()   bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val)   bfin_write32(SPORT0_RX, val)
#define pSPORT0_RCR1   ((uint16_t volatile *)SPORT0_RCR1)
#define bfin_read_SPORT0_RCR1()   bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val)   bfin_write16(SPORT0_RCR1, val)
#define pSPORT0_RCR2   ((uint16_t volatile *)SPORT0_RCR2)
#define bfin_read_SPORT0_RCR2()   bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val)   bfin_write16(SPORT0_RCR2, val)
#define pSPORT0_RCLKDIV   ((uint16_t volatile *)SPORT0_RCLKDIV)
#define bfin_read_SPORT0_RCLKDIV()   bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val)   bfin_write16(SPORT0_RCLKDIV, val)
#define pSPORT0_RFSDIV   ((uint16_t volatile *)SPORT0_RFSDIV)
#define bfin_read_SPORT0_RFSDIV()   bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val)   bfin_write16(SPORT0_RFSDIV, val)
#define pSPORT0_STAT   ((uint16_t volatile *)SPORT0_STAT)
#define bfin_read_SPORT0_STAT()   bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val)   bfin_write16(SPORT0_STAT, val)
#define pSPORT0_CHNL   ((uint16_t volatile *)SPORT0_CHNL)
#define bfin_read_SPORT0_CHNL()   bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val)   bfin_write16(SPORT0_CHNL, val)
#define pSPORT0_MCMC1   ((uint16_t volatile *)SPORT0_MCMC1)
#define bfin_read_SPORT0_MCMC1()   bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
#define pSPORT0_MCMC2   ((uint16_t volatile *)SPORT0_MCMC2)
#define bfin_read_SPORT0_MCMC2()   bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
#define pSPORT0_MTCS0   ((uint32_t volatile *)SPORT0_MTCS0)
#define bfin_read_SPORT0_MTCS0()   bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
#define pSPORT0_MTCS1   ((uint32_t volatile *)SPORT0_MTCS1)
#define bfin_read_SPORT0_MTCS1()   bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
#define pSPORT0_MTCS2   ((uint32_t volatile *)SPORT0_MTCS2)
#define bfin_read_SPORT0_MTCS2()   bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
#define pSPORT0_MTCS3   ((uint32_t volatile *)SPORT0_MTCS3)
#define bfin_read_SPORT0_MTCS3()   bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
#define pSPORT0_MRCS0   ((uint32_t volatile *)SPORT0_MRCS0)
#define bfin_read_SPORT0_MRCS0()   bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
#define pSPORT0_MRCS1   ((uint32_t volatile *)SPORT0_MRCS1)
#define bfin_read_SPORT0_MRCS1()   bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
#define pSPORT0_MRCS2   ((uint32_t volatile *)SPORT0_MRCS2)
#define bfin_read_SPORT0_MRCS2()   bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
#define pSPORT0_MRCS3   ((uint32_t volatile *)SPORT0_MRCS3)
#define bfin_read_SPORT0_MRCS3()   bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
#define pSPORT1_TCR1   ((uint16_t volatile *)SPORT1_TCR1)
#define bfin_read_SPORT1_TCR1()   bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val)   bfin_write16(SPORT1_TCR1, val)
#define pSPORT1_TCR2   ((uint16_t volatile *)SPORT1_TCR2)
#define bfin_read_SPORT1_TCR2()   bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val)   bfin_write16(SPORT1_TCR2, val)
#define pSPORT1_TCLKDIV   ((uint16_t volatile *)SPORT1_TCLKDIV)
#define bfin_read_SPORT1_TCLKDIV()   bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val)   bfin_write16(SPORT1_TCLKDIV, val)
#define pSPORT1_TFSDIV   ((uint16_t volatile *)SPORT1_TFSDIV)
#define bfin_read_SPORT1_TFSDIV()   bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val)   bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX   ((uint32_t volatile *)SPORT1_TX)
#define bfin_read_SPORT1_TX()   bfin_read32(SPORT1_TX)
#define bfin_write_SPORT1_TX(val)   bfin_write32(SPORT1_TX, val)
#define pSPORT1_RX   ((uint32_t volatile *)SPORT1_RX)
#define bfin_read_SPORT1_RX()   bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val)   bfin_write32(SPORT1_RX, val)
#define pSPORT1_RCR1   ((uint16_t volatile *)SPORT1_RCR1)
#define bfin_read_SPORT1_RCR1()   bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val)   bfin_write16(SPORT1_RCR1, val)
#define pSPORT1_RCR2   ((uint16_t volatile *)SPORT1_RCR2)
#define bfin_read_SPORT1_RCR2()   bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val)   bfin_write16(SPORT1_RCR2, val)
#define pSPORT1_RCLKDIV   ((uint16_t volatile *)SPORT1_RCLKDIV)
#define bfin_read_SPORT1_RCLKDIV()   bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val)   bfin_write16(SPORT1_RCLKDIV, val)
#define pSPORT1_RFSDIV   ((uint16_t volatile *)SPORT1_RFSDIV)
#define bfin_read_SPORT1_RFSDIV()   bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val)   bfin_write16(SPORT1_RFSDIV, val)
#define pSPORT1_STAT   ((uint16_t volatile *)SPORT1_STAT)
#define bfin_read_SPORT1_STAT()   bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val)   bfin_write16(SPORT1_STAT, val)
#define pSPORT1_CHNL   ((uint16_t volatile *)SPORT1_CHNL)
#define bfin_read_SPORT1_CHNL()   bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val)   bfin_write16(SPORT1_CHNL, val)
#define pSPORT1_MCMC1   ((uint16_t volatile *)SPORT1_MCMC1)
#define bfin_read_SPORT1_MCMC1()   bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
#define pSPORT1_MCMC2   ((uint16_t volatile *)SPORT1_MCMC2)
#define bfin_read_SPORT1_MCMC2()   bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
#define pSPORT1_MTCS0   ((uint32_t volatile *)SPORT1_MTCS0)
#define bfin_read_SPORT1_MTCS0()   bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
#define pSPORT1_MTCS1   ((uint32_t volatile *)SPORT1_MTCS1)
#define bfin_read_SPORT1_MTCS1()   bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
#define pSPORT1_MTCS2   ((uint32_t volatile *)SPORT1_MTCS2)
#define bfin_read_SPORT1_MTCS2()   bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
#define pSPORT1_MTCS3   ((uint32_t volatile *)SPORT1_MTCS3)
#define bfin_read_SPORT1_MTCS3()   bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
#define pSPORT1_MRCS0   ((uint32_t volatile *)SPORT1_MRCS0)
#define bfin_read_SPORT1_MRCS0()   bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
#define pSPORT1_MRCS1   ((uint32_t volatile *)SPORT1_MRCS1)
#define bfin_read_SPORT1_MRCS1()   bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
#define pSPORT1_MRCS2   ((uint32_t volatile *)SPORT1_MRCS2)
#define bfin_read_SPORT1_MRCS2()   bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
#define pSPORT1_MRCS3   ((uint32_t volatile *)SPORT1_MRCS3)
#define bfin_read_SPORT1_MRCS3()   bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
#define pEVT0   ((void * volatile *)EVT0)
#define bfin_read_EVT0()   bfin_readPTR(EVT0)
#define bfin_write_EVT0(val)   bfin_writePTR(EVT0, val)
#define pEVT1   ((void * volatile *)EVT1)
#define bfin_read_EVT1()   bfin_readPTR(EVT1)
#define bfin_write_EVT1(val)   bfin_writePTR(EVT1, val)
#define pEVT2   ((void * volatile *)EVT2)
#define bfin_read_EVT2()   bfin_readPTR(EVT2)
#define bfin_write_EVT2(val)   bfin_writePTR(EVT2, val)
#define pEVT3   ((void * volatile *)EVT3)
#define bfin_read_EVT3()   bfin_readPTR(EVT3)
#define bfin_write_EVT3(val)   bfin_writePTR(EVT3, val)
#define pEVT4   ((void * volatile *)EVT4)
#define bfin_read_EVT4()   bfin_readPTR(EVT4)
#define bfin_write_EVT4(val)   bfin_writePTR(EVT4, val)
#define pEVT5   ((void * volatile *)EVT5)
#define bfin_read_EVT5()   bfin_readPTR(EVT5)
#define bfin_write_EVT5(val)   bfin_writePTR(EVT5, val)
#define pEVT6   ((void * volatile *)EVT6)
#define bfin_read_EVT6()   bfin_readPTR(EVT6)
#define bfin_write_EVT6(val)   bfin_writePTR(EVT6, val)
#define pEVT7   ((void * volatile *)EVT7)
#define bfin_read_EVT7()   bfin_readPTR(EVT7)
#define bfin_write_EVT7(val)   bfin_writePTR(EVT7, val)
#define pEVT8   ((void * volatile *)EVT8)
#define bfin_read_EVT8()   bfin_readPTR(EVT8)
#define bfin_write_EVT8(val)   bfin_writePTR(EVT8, val)
#define pEVT9   ((void * volatile *)EVT9)
#define bfin_read_EVT9()   bfin_readPTR(EVT9)
#define bfin_write_EVT9(val)   bfin_writePTR(EVT9, val)
#define pEVT10   ((void * volatile *)EVT10)
#define bfin_read_EVT10()   bfin_readPTR(EVT10)
#define bfin_write_EVT10(val)   bfin_writePTR(EVT10, val)
#define pEVT11   ((void * volatile *)EVT11)
#define bfin_read_EVT11()   bfin_readPTR(EVT11)
#define bfin_write_EVT11(val)   bfin_writePTR(EVT11, val)
#define pEVT12   ((void * volatile *)EVT12)
#define bfin_read_EVT12()   bfin_readPTR(EVT12)
#define bfin_write_EVT12(val)   bfin_writePTR(EVT12, val)
#define pEVT13   ((void * volatile *)EVT13)
#define bfin_read_EVT13()   bfin_readPTR(EVT13)
#define bfin_write_EVT13(val)   bfin_writePTR(EVT13, val)
#define pEVT14   ((void * volatile *)EVT14)
#define bfin_read_EVT14()   bfin_readPTR(EVT14)
#define bfin_write_EVT14(val)   bfin_writePTR(EVT14, val)
#define pEVT15   ((void * volatile *)EVT15)
#define bfin_read_EVT15()   bfin_readPTR(EVT15)
#define bfin_write_EVT15(val)   bfin_writePTR(EVT15, val)
#define pILAT   ((uint32_t volatile *)ILAT)
#define bfin_read_ILAT()   bfin_read32(ILAT)
#define bfin_write_ILAT(val)   bfin_write32(ILAT, val)
#define pIMASK   ((uint32_t volatile *)IMASK)
#define bfin_read_IMASK()   bfin_read32(IMASK)
#define bfin_write_IMASK(val)   bfin_write32(IMASK, val)
#define pIPEND   ((uint32_t volatile *)IPEND)
#define bfin_read_IPEND()   bfin_read32(IPEND)
#define bfin_write_IPEND(val)   bfin_write32(IPEND, val)
#define pIPRIO   ((uint32_t volatile *)IPRIO)
#define bfin_read_IPRIO()   bfin_read32(IPRIO)
#define bfin_write_IPRIO(val)   bfin_write32(IPRIO, val)
#define pTCNTL   ((uint32_t volatile *)TCNTL)
#define bfin_read_TCNTL()   bfin_read32(TCNTL)
#define bfin_write_TCNTL(val)   bfin_write32(TCNTL, val)
#define pTPERIOD   ((uint32_t volatile *)TPERIOD)
#define bfin_read_TPERIOD()   bfin_read32(TPERIOD)
#define bfin_write_TPERIOD(val)   bfin_write32(TPERIOD, val)
#define pTSCALE   ((uint32_t volatile *)TSCALE)
#define bfin_read_TSCALE()   bfin_read32(TSCALE)
#define bfin_write_TSCALE(val)   bfin_write32(TSCALE, val)
#define pTCOUNT   ((uint32_t volatile *)TCOUNT)
#define bfin_read_TCOUNT()   bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val)   bfin_write32(TCOUNT, val)

Define Documentation

 
#define bfin_read_CHIPID (  )     bfin_read32(CHIPID)

 
#define bfin_read_DMA1_0_CONFIG (  )     bfin_read16(DMA1_0_CONFIG)

 
#define bfin_read_DMA1_0_CURR_ADDR (  )     bfin_readPTR(DMA1_0_CURR_ADDR)

 
#define bfin_read_DMA1_0_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_0_CURR_DESC_PTR)

 
#define bfin_read_DMA1_0_CURR_X_COUNT (  )     bfin_read16(DMA1_0_CURR_X_COUNT)

 
#define bfin_read_DMA1_0_CURR_Y_COUNT (  )     bfin_read16(DMA1_0_CURR_Y_COUNT)

 
#define bfin_read_DMA1_0_IRQ_STATUS (  )     bfin_read16(DMA1_0_IRQ_STATUS)

 
#define bfin_read_DMA1_0_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_0_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_0_PERIPHERAL_MAP (  )     bfin_read16(DMA1_0_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_0_START_ADDR (  )     bfin_readPTR(DMA1_0_START_ADDR)

 
#define bfin_read_DMA1_0_X_COUNT (  )     bfin_read16(DMA1_0_X_COUNT)

 
#define bfin_read_DMA1_0_X_MODIFY (  )     bfin_read16(DMA1_0_X_MODIFY)

 
#define bfin_read_DMA1_0_Y_COUNT (  )     bfin_read16(DMA1_0_Y_COUNT)

 
#define bfin_read_DMA1_0_Y_MODIFY (  )     bfin_read16(DMA1_0_Y_MODIFY)

 
#define bfin_read_DMA1_10_CONFIG (  )     bfin_read16(DMA1_10_CONFIG)

 
#define bfin_read_DMA1_10_CURR_ADDR (  )     bfin_readPTR(DMA1_10_CURR_ADDR)

 
#define bfin_read_DMA1_10_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_10_CURR_DESC_PTR)

 
#define bfin_read_DMA1_10_CURR_X_COUNT (  )     bfin_read16(DMA1_10_CURR_X_COUNT)

 
#define bfin_read_DMA1_10_CURR_Y_COUNT (  )     bfin_read16(DMA1_10_CURR_Y_COUNT)

 
#define bfin_read_DMA1_10_IRQ_STATUS (  )     bfin_read16(DMA1_10_IRQ_STATUS)

 
#define bfin_read_DMA1_10_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_10_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_10_PERIPHERAL_MAP (  )     bfin_read16(DMA1_10_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_10_START_ADDR (  )     bfin_readPTR(DMA1_10_START_ADDR)

 
#define bfin_read_DMA1_10_X_COUNT (  )     bfin_read16(DMA1_10_X_COUNT)

 
#define bfin_read_DMA1_10_X_MODIFY (  )     bfin_read16(DMA1_10_X_MODIFY)

 
#define bfin_read_DMA1_10_Y_COUNT (  )     bfin_read16(DMA1_10_Y_COUNT)

 
#define bfin_read_DMA1_10_Y_MODIFY (  )     bfin_read16(DMA1_10_Y_MODIFY)

 
#define bfin_read_DMA1_11_CONFIG (  )     bfin_read16(DMA1_11_CONFIG)

 
#define bfin_read_DMA1_11_CURR_ADDR (  )     bfin_readPTR(DMA1_11_CURR_ADDR)

 
#define bfin_read_DMA1_11_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_11_CURR_DESC_PTR)

 
#define bfin_read_DMA1_11_CURR_X_COUNT (  )     bfin_read16(DMA1_11_CURR_X_COUNT)

 
#define bfin_read_DMA1_11_CURR_Y_COUNT (  )     bfin_read16(DMA1_11_CURR_Y_COUNT)

 
#define bfin_read_DMA1_11_IRQ_STATUS (  )     bfin_read16(DMA1_11_IRQ_STATUS)

 
#define bfin_read_DMA1_11_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_11_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_11_PERIPHERAL_MAP (  )     bfin_read16(DMA1_11_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_11_START_ADDR (  )     bfin_readPTR(DMA1_11_START_ADDR)

 
#define bfin_read_DMA1_11_X_COUNT (  )     bfin_read16(DMA1_11_X_COUNT)

 
#define bfin_read_DMA1_11_X_MODIFY (  )     bfin_read16(DMA1_11_X_MODIFY)

 
#define bfin_read_DMA1_11_Y_COUNT (  )     bfin_read16(DMA1_11_Y_COUNT)

 
#define bfin_read_DMA1_11_Y_MODIFY (  )     bfin_read16(DMA1_11_Y_MODIFY)

 
#define bfin_read_DMA1_1_CONFIG (  )     bfin_read16(DMA1_1_CONFIG)

 
#define bfin_read_DMA1_1_CURR_ADDR (  )     bfin_readPTR(DMA1_1_CURR_ADDR)

 
#define bfin_read_DMA1_1_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_1_CURR_DESC_PTR)

 
#define bfin_read_DMA1_1_CURR_X_COUNT (  )     bfin_read16(DMA1_1_CURR_X_COUNT)

 
#define bfin_read_DMA1_1_CURR_Y_COUNT (  )     bfin_read16(DMA1_1_CURR_Y_COUNT)

 
#define bfin_read_DMA1_1_IRQ_STATUS (  )     bfin_read16(DMA1_1_IRQ_STATUS)

 
#define bfin_read_DMA1_1_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_1_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_1_PERIPHERAL_MAP (  )     bfin_read16(DMA1_1_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_1_START_ADDR (  )     bfin_readPTR(DMA1_1_START_ADDR)

 
#define bfin_read_DMA1_1_X_COUNT (  )     bfin_read16(DMA1_1_X_COUNT)

 
#define bfin_read_DMA1_1_X_MODIFY (  )     bfin_read16(DMA1_1_X_MODIFY)

 
#define bfin_read_DMA1_1_Y_COUNT (  )     bfin_read16(DMA1_1_Y_COUNT)

 
#define bfin_read_DMA1_1_Y_MODIFY (  )     bfin_read16(DMA1_1_Y_MODIFY)

 
#define bfin_read_DMA1_2_CONFIG (  )     bfin_read16(DMA1_2_CONFIG)

 
#define bfin_read_DMA1_2_CURR_ADDR (  )     bfin_readPTR(DMA1_2_CURR_ADDR)

 
#define bfin_read_DMA1_2_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_2_CURR_DESC_PTR)

 
#define bfin_read_DMA1_2_CURR_X_COUNT (  )     bfin_read16(DMA1_2_CURR_X_COUNT)

 
#define bfin_read_DMA1_2_CURR_Y_COUNT (  )     bfin_read16(DMA1_2_CURR_Y_COUNT)

 
#define bfin_read_DMA1_2_IRQ_STATUS (  )     bfin_read16(DMA1_2_IRQ_STATUS)

 
#define bfin_read_DMA1_2_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_2_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_2_PERIPHERAL_MAP (  )     bfin_read16(DMA1_2_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_2_START_ADDR (  )     bfin_readPTR(DMA1_2_START_ADDR)

 
#define bfin_read_DMA1_2_X_COUNT (  )     bfin_read16(DMA1_2_X_COUNT)

 
#define bfin_read_DMA1_2_X_MODIFY (  )     bfin_read16(DMA1_2_X_MODIFY)

 
#define bfin_read_DMA1_2_Y_COUNT (  )     bfin_read16(DMA1_2_Y_COUNT)

 
#define bfin_read_DMA1_2_Y_MODIFY (  )     bfin_read16(DMA1_2_Y_MODIFY)

 
#define bfin_read_DMA1_3_CONFIG (  )     bfin_read16(DMA1_3_CONFIG)

 
#define bfin_read_DMA1_3_CURR_ADDR (  )     bfin_readPTR(DMA1_3_CURR_ADDR)

 
#define bfin_read_DMA1_3_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_3_CURR_DESC_PTR)

 
#define bfin_read_DMA1_3_CURR_X_COUNT (  )     bfin_read16(DMA1_3_CURR_X_COUNT)

 
#define bfin_read_DMA1_3_CURR_Y_COUNT (  )     bfin_read16(DMA1_3_CURR_Y_COUNT)

 
#define bfin_read_DMA1_3_IRQ_STATUS (  )     bfin_read16(DMA1_3_IRQ_STATUS)

 
#define bfin_read_DMA1_3_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_3_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_3_PERIPHERAL_MAP (  )     bfin_read16(DMA1_3_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_3_START_ADDR (  )     bfin_readPTR(DMA1_3_START_ADDR)

 
#define bfin_read_DMA1_3_X_COUNT (  )     bfin_read16(DMA1_3_X_COUNT)

 
#define bfin_read_DMA1_3_X_MODIFY (  )     bfin_read16(DMA1_3_X_MODIFY)

 
#define bfin_read_DMA1_3_Y_COUNT (  )     bfin_read16(DMA1_3_Y_COUNT)

 
#define bfin_read_DMA1_3_Y_MODIFY (  )     bfin_read16(DMA1_3_Y_MODIFY)

 
#define bfin_read_DMA1_4_CONFIG (  )     bfin_read16(DMA1_4_CONFIG)

 
#define bfin_read_DMA1_4_CURR_ADDR (  )     bfin_readPTR(DMA1_4_CURR_ADDR)

 
#define bfin_read_DMA1_4_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_4_CURR_DESC_PTR)

 
#define bfin_read_DMA1_4_CURR_X_COUNT (  )     bfin_read16(DMA1_4_CURR_X_COUNT)

 
#define bfin_read_DMA1_4_CURR_Y_COUNT (  )     bfin_read16(DMA1_4_CURR_Y_COUNT)

 
#define bfin_read_DMA1_4_IRQ_STATUS (  )     bfin_read16(DMA1_4_IRQ_STATUS)

 
#define bfin_read_DMA1_4_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_4_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_4_PERIPHERAL_MAP (  )     bfin_read16(DMA1_4_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_4_START_ADDR (  )     bfin_readPTR(DMA1_4_START_ADDR)

 
#define bfin_read_DMA1_4_X_COUNT (  )     bfin_read16(DMA1_4_X_COUNT)

 
#define bfin_read_DMA1_4_X_MODIFY (  )     bfin_read16(DMA1_4_X_MODIFY)

 
#define bfin_read_DMA1_4_Y_COUNT (  )     bfin_read16(DMA1_4_Y_COUNT)

 
#define bfin_read_DMA1_4_Y_MODIFY (  )     bfin_read16(DMA1_4_Y_MODIFY)

 
#define bfin_read_DMA1_5_CONFIG (  )     bfin_read16(DMA1_5_CONFIG)

 
#define bfin_read_DMA1_5_CURR_ADDR (  )     bfin_readPTR(DMA1_5_CURR_ADDR)

 
#define bfin_read_DMA1_5_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_5_CURR_DESC_PTR)

 
#define bfin_read_DMA1_5_CURR_X_COUNT (  )     bfin_read16(DMA1_5_CURR_X_COUNT)

 
#define bfin_read_DMA1_5_CURR_Y_COUNT (  )     bfin_read16(DMA1_5_CURR_Y_COUNT)

 
#define bfin_read_DMA1_5_IRQ_STATUS (  )     bfin_read16(DMA1_5_IRQ_STATUS)

 
#define bfin_read_DMA1_5_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_5_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_5_PERIPHERAL_MAP (  )     bfin_read16(DMA1_5_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_5_START_ADDR (  )     bfin_readPTR(DMA1_5_START_ADDR)

 
#define bfin_read_DMA1_5_X_COUNT (  )     bfin_read16(DMA1_5_X_COUNT)

 
#define bfin_read_DMA1_5_X_MODIFY (  )     bfin_read16(DMA1_5_X_MODIFY)

 
#define bfin_read_DMA1_5_Y_COUNT (  )     bfin_read16(DMA1_5_Y_COUNT)

 
#define bfin_read_DMA1_5_Y_MODIFY (  )     bfin_read16(DMA1_5_Y_MODIFY)

 
#define bfin_read_DMA1_6_CONFIG (  )     bfin_read16(DMA1_6_CONFIG)

 
#define bfin_read_DMA1_6_CURR_ADDR (  )     bfin_readPTR(DMA1_6_CURR_ADDR)

 
#define bfin_read_DMA1_6_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_6_CURR_DESC_PTR)

 
#define bfin_read_DMA1_6_CURR_X_COUNT (  )     bfin_read16(DMA1_6_CURR_X_COUNT)

 
#define bfin_read_DMA1_6_CURR_Y_COUNT (  )     bfin_read16(DMA1_6_CURR_Y_COUNT)

 
#define bfin_read_DMA1_6_IRQ_STATUS (  )     bfin_read16(DMA1_6_IRQ_STATUS)

 
#define bfin_read_DMA1_6_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_6_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_6_PERIPHERAL_MAP (  )     bfin_read16(DMA1_6_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_6_START_ADDR (  )     bfin_readPTR(DMA1_6_START_ADDR)

 
#define bfin_read_DMA1_6_X_COUNT (  )     bfin_read16(DMA1_6_X_COUNT)

 
#define bfin_read_DMA1_6_X_MODIFY (  )     bfin_read16(DMA1_6_X_MODIFY)

 
#define bfin_read_DMA1_6_Y_COUNT (  )     bfin_read16(DMA1_6_Y_COUNT)

 
#define bfin_read_DMA1_6_Y_MODIFY (  )     bfin_read16(DMA1_6_Y_MODIFY)

 
#define bfin_read_DMA1_7_CONFIG (  )     bfin_read16(DMA1_7_CONFIG)

 
#define bfin_read_DMA1_7_CURR_ADDR (  )     bfin_readPTR(DMA1_7_CURR_ADDR)

 
#define bfin_read_DMA1_7_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_7_CURR_DESC_PTR)

 
#define bfin_read_DMA1_7_CURR_X_COUNT (  )     bfin_read16(DMA1_7_CURR_X_COUNT)

 
#define bfin_read_DMA1_7_CURR_Y_COUNT (  )     bfin_read16(DMA1_7_CURR_Y_COUNT)

 
#define bfin_read_DMA1_7_IRQ_STATUS (  )     bfin_read16(DMA1_7_IRQ_STATUS)

 
#define bfin_read_DMA1_7_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_7_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_7_PERIPHERAL_MAP (  )     bfin_read16(DMA1_7_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_7_START_ADDR (  )     bfin_readPTR(DMA1_7_START_ADDR)

 
#define bfin_read_DMA1_7_X_COUNT (  )     bfin_read16(DMA1_7_X_COUNT)

 
#define bfin_read_DMA1_7_X_MODIFY (  )     bfin_read16(DMA1_7_X_MODIFY)

 
#define bfin_read_DMA1_7_Y_COUNT (  )     bfin_read16(DMA1_7_Y_COUNT)

 
#define bfin_read_DMA1_7_Y_MODIFY (  )     bfin_read16(DMA1_7_Y_MODIFY)

 
#define bfin_read_DMA1_8_CONFIG (  )     bfin_read16(DMA1_8_CONFIG)

 
#define bfin_read_DMA1_8_CURR_ADDR (  )     bfin_readPTR(DMA1_8_CURR_ADDR)

 
#define bfin_read_DMA1_8_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_8_CURR_DESC_PTR)

 
#define bfin_read_DMA1_8_CURR_X_COUNT (  )     bfin_read16(DMA1_8_CURR_X_COUNT)

 
#define bfin_read_DMA1_8_CURR_Y_COUNT (  )     bfin_read16(DMA1_8_CURR_Y_COUNT)

 
#define bfin_read_DMA1_8_IRQ_STATUS (  )     bfin_read16(DMA1_8_IRQ_STATUS)

 
#define bfin_read_DMA1_8_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_8_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_8_PERIPHERAL_MAP (  )     bfin_read16(DMA1_8_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_8_START_ADDR (  )     bfin_readPTR(DMA1_8_START_ADDR)

 
#define bfin_read_DMA1_8_X_COUNT (  )     bfin_read16(DMA1_8_X_COUNT)

 
#define bfin_read_DMA1_8_X_MODIFY (  )     bfin_read16(DMA1_8_X_MODIFY)

 
#define bfin_read_DMA1_8_Y_COUNT (  )     bfin_read16(DMA1_8_Y_COUNT)

 
#define bfin_read_DMA1_8_Y_MODIFY (  )     bfin_read16(DMA1_8_Y_MODIFY)

 
#define bfin_read_DMA1_9_CONFIG (  )     bfin_read16(DMA1_9_CONFIG)

 
#define bfin_read_DMA1_9_CURR_ADDR (  )     bfin_readPTR(DMA1_9_CURR_ADDR)

 
#define bfin_read_DMA1_9_CURR_DESC_PTR (  )     bfin_readPTR(DMA1_9_CURR_DESC_PTR)

 
#define bfin_read_DMA1_9_CURR_X_COUNT (  )     bfin_read16(DMA1_9_CURR_X_COUNT)

 
#define bfin_read_DMA1_9_CURR_Y_COUNT (  )     bfin_read16(DMA1_9_CURR_Y_COUNT)

 
#define bfin_read_DMA1_9_IRQ_STATUS (  )     bfin_read16(DMA1_9_IRQ_STATUS)

 
#define bfin_read_DMA1_9_NEXT_DESC_PTR (  )     bfin_readPTR(DMA1_9_NEXT_DESC_PTR)

 
#define bfin_read_DMA1_9_PERIPHERAL_MAP (  )     bfin_read16(DMA1_9_PERIPHERAL_MAP)

 
#define bfin_read_DMA1_9_START_ADDR (  )     bfin_readPTR(DMA1_9_START_ADDR)

 
#define bfin_read_DMA1_9_X_COUNT (  )     bfin_read16(DMA1_9_X_COUNT)

 
#define bfin_read_DMA1_9_X_MODIFY (  )     bfin_read16(DMA1_9_X_MODIFY)

 
#define bfin_read_DMA1_9_Y_COUNT (  )     bfin_read16(DMA1_9_Y_COUNT)

 
#define bfin_read_DMA1_9_Y_MODIFY (  )     bfin_read16(DMA1_9_Y_MODIFY)

 
#define bfin_read_DMA1_TC_CNT (  )     bfin_read16(DMA1_TC_CNT)

 
#define bfin_read_DMA1_TC_PER (  )     bfin_read16(DMA1_TC_PER)

 
#define bfin_read_DMA2_0_CONFIG (  )     bfin_read16(DMA2_0_CONFIG)

 
#define bfin_read_DMA2_0_CURR_ADDR (  )     bfin_readPTR(DMA2_0_CURR_ADDR)

 
#define bfin_read_DMA2_0_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_0_CURR_DESC_PTR)

 
#define bfin_read_DMA2_0_CURR_X_COUNT (  )     bfin_read16(DMA2_0_CURR_X_COUNT)

 
#define bfin_read_DMA2_0_CURR_Y_COUNT (  )     bfin_read16(DMA2_0_CURR_Y_COUNT)

 
#define bfin_read_DMA2_0_IRQ_STATUS (  )     bfin_read16(DMA2_0_IRQ_STATUS)

 
#define bfin_read_DMA2_0_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_0_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_0_PERIPHERAL_MAP (  )     bfin_read16(DMA2_0_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_0_START_ADDR (  )     bfin_readPTR(DMA2_0_START_ADDR)

 
#define bfin_read_DMA2_0_X_COUNT (  )     bfin_read16(DMA2_0_X_COUNT)

 
#define bfin_read_DMA2_0_X_MODIFY (  )     bfin_read16(DMA2_0_X_MODIFY)

 
#define bfin_read_DMA2_0_Y_COUNT (  )     bfin_read16(DMA2_0_Y_COUNT)

 
#define bfin_read_DMA2_0_Y_MODIFY (  )     bfin_read16(DMA2_0_Y_MODIFY)

 
#define bfin_read_DMA2_10_CONFIG (  )     bfin_read16(DMA2_10_CONFIG)

 
#define bfin_read_DMA2_10_CURR_ADDR (  )     bfin_readPTR(DMA2_10_CURR_ADDR)

 
#define bfin_read_DMA2_10_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_10_CURR_DESC_PTR)

 
#define bfin_read_DMA2_10_CURR_X_COUNT (  )     bfin_read16(DMA2_10_CURR_X_COUNT)

 
#define bfin_read_DMA2_10_CURR_Y_COUNT (  )     bfin_read16(DMA2_10_CURR_Y_COUNT)

 
#define bfin_read_DMA2_10_IRQ_STATUS (  )     bfin_read16(DMA2_10_IRQ_STATUS)

 
#define bfin_read_DMA2_10_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_10_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_10_PERIPHERAL_MAP (  )     bfin_read16(DMA2_10_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_10_START_ADDR (  )     bfin_readPTR(DMA2_10_START_ADDR)

 
#define bfin_read_DMA2_10_X_COUNT (  )     bfin_read16(DMA2_10_X_COUNT)

 
#define bfin_read_DMA2_10_X_MODIFY (  )     bfin_read16(DMA2_10_X_MODIFY)

 
#define bfin_read_DMA2_10_Y_COUNT (  )     bfin_read16(DMA2_10_Y_COUNT)

 
#define bfin_read_DMA2_10_Y_MODIFY (  )     bfin_read16(DMA2_10_Y_MODIFY)

 
#define bfin_read_DMA2_11_CONFIG (  )     bfin_read16(DMA2_11_CONFIG)

 
#define bfin_read_DMA2_11_CURR_ADDR (  )     bfin_readPTR(DMA2_11_CURR_ADDR)

 
#define bfin_read_DMA2_11_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_11_CURR_DESC_PTR)

 
#define bfin_read_DMA2_11_CURR_X_COUNT (  )     bfin_read16(DMA2_11_CURR_X_COUNT)

 
#define bfin_read_DMA2_11_CURR_Y_COUNT (  )     bfin_read16(DMA2_11_CURR_Y_COUNT)

 
#define bfin_read_DMA2_11_IRQ_STATUS (  )     bfin_read16(DMA2_11_IRQ_STATUS)

 
#define bfin_read_DMA2_11_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_11_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_11_PERIPHERAL_MAP (  )     bfin_read16(DMA2_11_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_11_START_ADDR (  )     bfin_readPTR(DMA2_11_START_ADDR)

 
#define bfin_read_DMA2_11_X_COUNT (  )     bfin_read16(DMA2_11_X_COUNT)

 
#define bfin_read_DMA2_11_X_MODIFY (  )     bfin_read16(DMA2_11_X_MODIFY)

 
#define bfin_read_DMA2_11_Y_COUNT (  )     bfin_read16(DMA2_11_Y_COUNT)

 
#define bfin_read_DMA2_11_Y_MODIFY (  )     bfin_read16(DMA2_11_Y_MODIFY)

 
#define bfin_read_DMA2_1_CONFIG (  )     bfin_read16(DMA2_1_CONFIG)

 
#define bfin_read_DMA2_1_CURR_ADDR (  )     bfin_readPTR(DMA2_1_CURR_ADDR)

 
#define bfin_read_DMA2_1_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_1_CURR_DESC_PTR)

 
#define bfin_read_DMA2_1_CURR_X_COUNT (  )     bfin_read16(DMA2_1_CURR_X_COUNT)

 
#define bfin_read_DMA2_1_CURR_Y_COUNT (  )     bfin_read16(DMA2_1_CURR_Y_COUNT)

 
#define bfin_read_DMA2_1_IRQ_STATUS (  )     bfin_read16(DMA2_1_IRQ_STATUS)

 
#define bfin_read_DMA2_1_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_1_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_1_PERIPHERAL_MAP (  )     bfin_read16(DMA2_1_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_1_START_ADDR (  )     bfin_readPTR(DMA2_1_START_ADDR)

 
#define bfin_read_DMA2_1_X_COUNT (  )     bfin_read16(DMA2_1_X_COUNT)

 
#define bfin_read_DMA2_1_X_MODIFY (  )     bfin_read16(DMA2_1_X_MODIFY)

 
#define bfin_read_DMA2_1_Y_COUNT (  )     bfin_read16(DMA2_1_Y_COUNT)

 
#define bfin_read_DMA2_1_Y_MODIFY (  )     bfin_read16(DMA2_1_Y_MODIFY)

 
#define bfin_read_DMA2_2_CONFIG (  )     bfin_read16(DMA2_2_CONFIG)

 
#define bfin_read_DMA2_2_CURR_ADDR (  )     bfin_readPTR(DMA2_2_CURR_ADDR)

 
#define bfin_read_DMA2_2_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_2_CURR_DESC_PTR)

 
#define bfin_read_DMA2_2_CURR_X_COUNT (  )     bfin_read16(DMA2_2_CURR_X_COUNT)

 
#define bfin_read_DMA2_2_CURR_Y_COUNT (  )     bfin_read16(DMA2_2_CURR_Y_COUNT)

 
#define bfin_read_DMA2_2_IRQ_STATUS (  )     bfin_read16(DMA2_2_IRQ_STATUS)

 
#define bfin_read_DMA2_2_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_2_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_2_PERIPHERAL_MAP (  )     bfin_read16(DMA2_2_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_2_START_ADDR (  )     bfin_readPTR(DMA2_2_START_ADDR)

 
#define bfin_read_DMA2_2_X_COUNT (  )     bfin_read16(DMA2_2_X_COUNT)

 
#define bfin_read_DMA2_2_X_MODIFY (  )     bfin_read16(DMA2_2_X_MODIFY)

 
#define bfin_read_DMA2_2_Y_COUNT (  )     bfin_read16(DMA2_2_Y_COUNT)

 
#define bfin_read_DMA2_2_Y_MODIFY (  )     bfin_read16(DMA2_2_Y_MODIFY)

 
#define bfin_read_DMA2_3_CONFIG (  )     bfin_read16(DMA2_3_CONFIG)

 
#define bfin_read_DMA2_3_CURR_ADDR (  )     bfin_readPTR(DMA2_3_CURR_ADDR)

 
#define bfin_read_DMA2_3_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_3_CURR_DESC_PTR)

 
#define bfin_read_DMA2_3_CURR_X_COUNT (  )     bfin_read16(DMA2_3_CURR_X_COUNT)

 
#define bfin_read_DMA2_3_CURR_Y_COUNT (  )     bfin_read16(DMA2_3_CURR_Y_COUNT)

 
#define bfin_read_DMA2_3_IRQ_STATUS (  )     bfin_read16(DMA2_3_IRQ_STATUS)

 
#define bfin_read_DMA2_3_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_3_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_3_PERIPHERAL_MAP (  )     bfin_read16(DMA2_3_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_3_START_ADDR (  )     bfin_readPTR(DMA2_3_START_ADDR)

 
#define bfin_read_DMA2_3_X_COUNT (  )     bfin_read16(DMA2_3_X_COUNT)

 
#define bfin_read_DMA2_3_X_MODIFY (  )     bfin_read16(DMA2_3_X_MODIFY)

 
#define bfin_read_DMA2_3_Y_COUNT (  )     bfin_read16(DMA2_3_Y_COUNT)

 
#define bfin_read_DMA2_3_Y_MODIFY (  )     bfin_read16(DMA2_3_Y_MODIFY)

 
#define bfin_read_DMA2_4_CONFIG (  )     bfin_read16(DMA2_4_CONFIG)

 
#define bfin_read_DMA2_4_CURR_ADDR (  )     bfin_readPTR(DMA2_4_CURR_ADDR)

 
#define bfin_read_DMA2_4_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_4_CURR_DESC_PTR)

 
#define bfin_read_DMA2_4_CURR_X_COUNT (  )     bfin_read16(DMA2_4_CURR_X_COUNT)

 
#define bfin_read_DMA2_4_CURR_Y_COUNT (  )     bfin_read16(DMA2_4_CURR_Y_COUNT)

 
#define bfin_read_DMA2_4_IRQ_STATUS (  )     bfin_read16(DMA2_4_IRQ_STATUS)

 
#define bfin_read_DMA2_4_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_4_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_4_PERIPHERAL_MAP (  )     bfin_read16(DMA2_4_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_4_START_ADDR (  )     bfin_readPTR(DMA2_4_START_ADDR)

 
#define bfin_read_DMA2_4_X_COUNT (  )     bfin_read16(DMA2_4_X_COUNT)

 
#define bfin_read_DMA2_4_X_MODIFY (  )     bfin_read16(DMA2_4_X_MODIFY)

 
#define bfin_read_DMA2_4_Y_COUNT (  )     bfin_read16(DMA2_4_Y_COUNT)

 
#define bfin_read_DMA2_4_Y_MODIFY (  )     bfin_read16(DMA2_4_Y_MODIFY)

 
#define bfin_read_DMA2_5_CONFIG (  )     bfin_read16(DMA2_5_CONFIG)

 
#define bfin_read_DMA2_5_CURR_ADDR (  )     bfin_readPTR(DMA2_5_CURR_ADDR)

 
#define bfin_read_DMA2_5_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_5_CURR_DESC_PTR)

 
#define bfin_read_DMA2_5_CURR_X_COUNT (  )     bfin_read16(DMA2_5_CURR_X_COUNT)

 
#define bfin_read_DMA2_5_CURR_Y_COUNT (  )     bfin_read16(DMA2_5_CURR_Y_COUNT)

 
#define bfin_read_DMA2_5_IRQ_STATUS (  )     bfin_read16(DMA2_5_IRQ_STATUS)

 
#define bfin_read_DMA2_5_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_5_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_5_PERIPHERAL_MAP (  )     bfin_read16(DMA2_5_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_5_START_ADDR (  )     bfin_readPTR(DMA2_5_START_ADDR)

 
#define bfin_read_DMA2_5_X_COUNT (  )     bfin_read16(DMA2_5_X_COUNT)

 
#define bfin_read_DMA2_5_X_MODIFY (  )     bfin_read16(DMA2_5_X_MODIFY)

 
#define bfin_read_DMA2_5_Y_COUNT (  )     bfin_read16(DMA2_5_Y_COUNT)

 
#define bfin_read_DMA2_5_Y_MODIFY (  )     bfin_read16(DMA2_5_Y_MODIFY)

 
#define bfin_read_DMA2_6_CONFIG (  )     bfin_read16(DMA2_6_CONFIG)

 
#define bfin_read_DMA2_6_CURR_ADDR (  )     bfin_readPTR(DMA2_6_CURR_ADDR)

 
#define bfin_read_DMA2_6_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_6_CURR_DESC_PTR)

 
#define bfin_read_DMA2_6_CURR_X_COUNT (  )     bfin_read16(DMA2_6_CURR_X_COUNT)

 
#define bfin_read_DMA2_6_CURR_Y_COUNT (  )     bfin_read16(DMA2_6_CURR_Y_COUNT)

 
#define bfin_read_DMA2_6_IRQ_STATUS (  )     bfin_read16(DMA2_6_IRQ_STATUS)

 
#define bfin_read_DMA2_6_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_6_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_6_PERIPHERAL_MAP (  )     bfin_read16(DMA2_6_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_6_START_ADDR (  )     bfin_readPTR(DMA2_6_START_ADDR)

 
#define bfin_read_DMA2_6_X_COUNT (  )     bfin_read16(DMA2_6_X_COUNT)

 
#define bfin_read_DMA2_6_X_MODIFY (  )     bfin_read16(DMA2_6_X_MODIFY)

 
#define bfin_read_DMA2_6_Y_COUNT (  )     bfin_read16(DMA2_6_Y_COUNT)

 
#define bfin_read_DMA2_6_Y_MODIFY (  )     bfin_read16(DMA2_6_Y_MODIFY)

 
#define bfin_read_DMA2_7_CONFIG (  )     bfin_read16(DMA2_7_CONFIG)

 
#define bfin_read_DMA2_7_CURR_ADDR (  )     bfin_readPTR(DMA2_7_CURR_ADDR)

 
#define bfin_read_DMA2_7_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_7_CURR_DESC_PTR)

 
#define bfin_read_DMA2_7_CURR_X_COUNT (  )     bfin_read16(DMA2_7_CURR_X_COUNT)

 
#define bfin_read_DMA2_7_CURR_Y_COUNT (  )     bfin_read16(DMA2_7_CURR_Y_COUNT)

 
#define bfin_read_DMA2_7_IRQ_STATUS (  )     bfin_read16(DMA2_7_IRQ_STATUS)

 
#define bfin_read_DMA2_7_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_7_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_7_PERIPHERAL_MAP (  )     bfin_read16(DMA2_7_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_7_START_ADDR (  )     bfin_readPTR(DMA2_7_START_ADDR)

 
#define bfin_read_DMA2_7_X_COUNT (  )     bfin_read16(DMA2_7_X_COUNT)

 
#define bfin_read_DMA2_7_X_MODIFY (  )     bfin_read16(DMA2_7_X_MODIFY)

 
#define bfin_read_DMA2_7_Y_COUNT (  )     bfin_read16(DMA2_7_Y_COUNT)

 
#define bfin_read_DMA2_7_Y_MODIFY (  )     bfin_read16(DMA2_7_Y_MODIFY)

 
#define bfin_read_DMA2_8_CONFIG (  )     bfin_read16(DMA2_8_CONFIG)

 
#define bfin_read_DMA2_8_CURR_ADDR (  )     bfin_readPTR(DMA2_8_CURR_ADDR)

 
#define bfin_read_DMA2_8_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_8_CURR_DESC_PTR)

 
#define bfin_read_DMA2_8_CURR_X_COUNT (  )     bfin_read16(DMA2_8_CURR_X_COUNT)

 
#define bfin_read_DMA2_8_CURR_Y_COUNT (  )     bfin_read16(DMA2_8_CURR_Y_COUNT)

 
#define bfin_read_DMA2_8_IRQ_STATUS (  )     bfin_read16(DMA2_8_IRQ_STATUS)

 
#define bfin_read_DMA2_8_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_8_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_8_PERIPHERAL_MAP (  )     bfin_read16(DMA2_8_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_8_START_ADDR (  )     bfin_readPTR(DMA2_8_START_ADDR)

 
#define bfin_read_DMA2_8_X_COUNT (  )     bfin_read16(DMA2_8_X_COUNT)

 
#define bfin_read_DMA2_8_X_MODIFY (  )     bfin_read16(DMA2_8_X_MODIFY)

 
#define bfin_read_DMA2_8_Y_COUNT (  )     bfin_read16(DMA2_8_Y_COUNT)

 
#define bfin_read_DMA2_8_Y_MODIFY (  )     bfin_read16(DMA2_8_Y_MODIFY)

 
#define bfin_read_DMA2_9_CONFIG (  )     bfin_read16(DMA2_9_CONFIG)

 
#define bfin_read_DMA2_9_CURR_ADDR (  )     bfin_readPTR(DMA2_9_CURR_ADDR)

 
#define bfin_read_DMA2_9_CURR_DESC_PTR (  )     bfin_readPTR(DMA2_9_CURR_DESC_PTR)

 
#define bfin_read_DMA2_9_CURR_X_COUNT (  )     bfin_read16(DMA2_9_CURR_X_COUNT)

 
#define bfin_read_DMA2_9_CURR_Y_COUNT (  )     bfin_read16(DMA2_9_CURR_Y_COUNT)

 
#define bfin_read_DMA2_9_IRQ_STATUS (  )     bfin_read16(DMA2_9_IRQ_STATUS)

 
#define bfin_read_DMA2_9_NEXT_DESC_PTR (  )     bfin_readPTR(DMA2_9_NEXT_DESC_PTR)

 
#define bfin_read_DMA2_9_PERIPHERAL_MAP (  )     bfin_read16(DMA2_9_PERIPHERAL_MAP)

 
#define bfin_read_DMA2_9_START_ADDR (  )     bfin_readPTR(DMA2_9_START_ADDR)

 
#define bfin_read_DMA2_9_X_COUNT (  )     bfin_read16(DMA2_9_X_COUNT)

 
#define bfin_read_DMA2_9_X_MODIFY (  )     bfin_read16(DMA2_9_X_MODIFY)

 
#define bfin_read_DMA2_9_Y_COUNT (  )     bfin_read16(DMA2_9_Y_COUNT)

 
#define bfin_read_DMA2_9_Y_MODIFY (  )     bfin_read16(DMA2_9_Y_MODIFY)

 
#define bfin_read_DMA2_TC_CNT (  )     bfin_read16(DMA2_TC_CNT)

 
#define bfin_read_DMA2_TC_PER (  )     bfin_read16(DMA2_TC_PER)

 
#define bfin_read_EVT0 (  )     bfin_readPTR(EVT0)

 
#define bfin_read_EVT1 (  )     bfin_readPTR(EVT1)

 
#define bfin_read_EVT10 (  )     bfin_readPTR(EVT10)

 
#define bfin_read_EVT11 (  )     bfin_readPTR(EVT11)

 
#define bfin_read_EVT12 (  )     bfin_readPTR(EVT12)

 
#define bfin_read_EVT13 (  )     bfin_readPTR(EVT13)

 
#define bfin_read_EVT14 (  )     bfin_readPTR(EVT14)

 
#define bfin_read_EVT15 (  )     bfin_readPTR(EVT15)

 
#define bfin_read_EVT2 (  )     bfin_readPTR(EVT2)

 
#define bfin_read_EVT3 (  )     bfin_readPTR(EVT3)

 
#define bfin_read_EVT4 (  )     bfin_readPTR(EVT4)

 
#define bfin_read_EVT5 (  )     bfin_readPTR(EVT5)

 
#define bfin_read_EVT6 (  )     bfin_readPTR(EVT6)

 
#define bfin_read_EVT7 (  )     bfin_readPTR(EVT7)

 
#define bfin_read_EVT8 (  )     bfin_readPTR(EVT8)

 
#define bfin_read_EVT9 (  )     bfin_readPTR(EVT9)

 
#define bfin_read_FIO0_BOTH (  )     bfin_read16(FIO0_BOTH)

 
#define bfin_read_FIO0_DIR (  )     bfin_read16(FIO0_DIR)

 
#define bfin_read_FIO0_EDGE (  )     bfin_read16(FIO0_EDGE)

 
#define bfin_read_FIO0_FLAG_C (  )     bfin_read16(FIO0_FLAG_C)

 
#define bfin_read_FIO0_FLAG_D (  )     bfin_read16(FIO0_FLAG_D)

 
#define bfin_read_FIO0_FLAG_S (  )     bfin_read16(FIO0_FLAG_S)

 
#define bfin_read_FIO0_FLAG_T (  )     bfin_read16(FIO0_FLAG_T)

 
#define bfin_read_FIO0_INEN (  )     bfin_read16(FIO0_INEN)

 
#define bfin_read_FIO0_MASKA_C (  )     bfin_read16(FIO0_MASKA_C)

 
#define bfin_read_FIO0_MASKA_D (  )     bfin_read16(FIO0_MASKA_D)

 
#define bfin_read_FIO0_MASKA_S (  )     bfin_read16(FIO0_MASKA_S)

 
#define bfin_read_FIO0_MASKA_T (  )     bfin_read16(FIO0_MASKA_T)

 
#define bfin_read_FIO0_MASKB_C (  )     bfin_read16(FIO0_MASKB_C)

 
#define bfin_read_FIO0_MASKB_D (  )     bfin_read16(FIO0_MASKB_D)

 
#define bfin_read_FIO0_MASKB_S (  )     bfin_read16(FIO0_MASKB_S)

 
#define bfin_read_FIO0_MASKB_T (  )     bfin_read16(FIO0_MASKB_T)

 
#define bfin_read_FIO0_POLAR (  )     bfin_read16(FIO0_POLAR)

 
#define bfin_read_FIO1_BOTH (  )     bfin_read16(FIO1_BOTH)

 
#define bfin_read_FIO1_DIR (  )     bfin_read16(FIO1_DIR)

 
#define bfin_read_FIO1_EDGE (  )     bfin_read16(FIO1_EDGE)

 
#define bfin_read_FIO1_FLAG_C (  )     bfin_read16(FIO1_FLAG_C)

 
#define bfin_read_FIO1_FLAG_D (  )     bfin_read16(FIO1_FLAG_D)

 
#define bfin_read_FIO1_FLAG_S (  )     bfin_read16(FIO1_FLAG_S)

 
#define bfin_read_FIO1_FLAG_T (  )     bfin_read16(FIO1_FLAG_T)

 
#define bfin_read_FIO1_INEN (  )     bfin_read16(FIO1_INEN)

 
#define bfin_read_FIO1_MASKA_C (  )     bfin_read16(FIO1_MASKA_C)

 
#define bfin_read_FIO1_MASKA_D (  )     bfin_read16(FIO1_MASKA_D)

 
#define bfin_read_FIO1_MASKA_S (  )     bfin_read16(FIO1_MASKA_S)

 
#define bfin_read_FIO1_MASKA_T (  )     bfin_read16(FIO1_MASKA_T)

 
#define bfin_read_FIO1_MASKB_C (  )     bfin_read16(FIO1_MASKB_C)

 
#define bfin_read_FIO1_MASKB_D (  )     bfin_read16(FIO1_MASKB_D)

 
#define bfin_read_FIO1_MASKB_S (  )     bfin_read16(FIO1_MASKB_S)

 
#define bfin_read_FIO1_MASKB_T (  )     bfin_read16(FIO1_MASKB_T)

 
#define bfin_read_FIO1_POLAR (  )     bfin_read16(FIO1_POLAR)

 
#define bfin_read_FIO2_BOTH (  )     bfin_read16(FIO2_BOTH)

 
#define bfin_read_FIO2_DIR (  )     bfin_read16(FIO2_DIR)

 
#define bfin_read_FIO2_EDGE (  )     bfin_read16(FIO2_EDGE)

 
#define bfin_read_FIO2_FLAG_C (  )     bfin_read16(FIO2_FLAG_C)

 
#define bfin_read_FIO2_FLAG_D (  )     bfin_read16(FIO2_FLAG_D)

 
#define bfin_read_FIO2_FLAG_S (  )     bfin_read16(FIO2_FLAG_S)

 
#define bfin_read_FIO2_FLAG_T (  )     bfin_read16(FIO2_FLAG_T)

 
#define bfin_read_FIO2_INEN (  )     bfin_read16(FIO2_INEN)

 
#define bfin_read_FIO2_MASKA_C (  )     bfin_read16(FIO2_MASKA_C)

 
#define bfin_read_FIO2_MASKA_D (  )     bfin_read16(FIO2_MASKA_D)

 
#define bfin_read_FIO2_MASKA_S (  )     bfin_read16(FIO2_MASKA_S)

 
#define bfin_read_FIO2_MASKA_T (  )     bfin_read16(FIO2_MASKA_T)

 
#define bfin_read_FIO2_MASKB_C (  )     bfin_read16(FIO2_MASKB_C)

 
#define bfin_read_FIO2_MASKB_D (  )     bfin_read16(FIO2_MASKB_D)

 
#define bfin_read_FIO2_MASKB_S (  )     bfin_read16(FIO2_MASKB_S)

 
#define bfin_read_FIO2_MASKB_T (  )     bfin_read16(FIO2_MASKB_T)

 
#define bfin_read_FIO2_POLAR (  )     bfin_read16(FIO2_POLAR)

 
#define bfin_read_ILAT (  )     bfin_read32(ILAT)

 
#define bfin_read_IMASK (  )     bfin_read32(IMASK)

 
#define bfin_read_IMDMA_D0_CONFIG (  )     bfin_read16(IMDMA_D0_CONFIG)

 
#define bfin_read_IMDMA_D0_CURR_ADDR (  )     bfin_readPTR(IMDMA_D0_CURR_ADDR)

 
#define bfin_read_IMDMA_D0_CURR_DESC_PTR (  )     bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)

 
#define bfin_read_IMDMA_D0_CURR_X_COUNT (  )     bfin_read16(IMDMA_D0_CURR_X_COUNT)

 
#define bfin_read_IMDMA_D0_CURR_Y_COUNT (  )     bfin_read16(IMDMA_D0_CURR_Y_COUNT)

 
#define bfin_read_IMDMA_D0_IRQ_STATUS (  )     bfin_read16(IMDMA_D0_IRQ_STATUS)

 
#define bfin_read_IMDMA_D0_NEXT_DESC_PTR (  )     bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)

 
#define bfin_read_IMDMA_D0_START_ADDR (  )     bfin_readPTR(IMDMA_D0_START_ADDR)

 
#define bfin_read_IMDMA_D0_X_COUNT (  )     bfin_read16(IMDMA_D0_X_COUNT)

 
#define bfin_read_IMDMA_D0_X_MODIFY (  )     bfin_read16(IMDMA_D0_X_MODIFY)

 
#define bfin_read_IMDMA_D0_Y_COUNT (  )     bfin_read16(IMDMA_D0_Y_COUNT)

 
#define bfin_read_IMDMA_D0_Y_MODIFY (  )     bfin_read16(IMDMA_D0_Y_MODIFY)

 
#define bfin_read_IMDMA_D1_CONFIG (  )     bfin_read16(IMDMA_D1_CONFIG)

 
#define bfin_read_IMDMA_D1_CURR_ADDR (  )     bfin_readPTR(IMDMA_D1_CURR_ADDR)

 
#define bfin_read_IMDMA_D1_CURR_DESC_PTR (  )     bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)

 
#define bfin_read_IMDMA_D1_CURR_X_COUNT (  )     bfin_read16(IMDMA_D1_CURR_X_COUNT)

 
#define bfin_read_IMDMA_D1_CURR_Y_COUNT (  )     bfin_read16(IMDMA_D1_CURR_Y_COUNT)

 
#define bfin_read_IMDMA_D1_IRQ_STATUS (  )     bfin_read16(IMDMA_D1_IRQ_STATUS)

 
#define bfin_read_IMDMA_D1_NEXT_DESC_PTR (  )     bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)

 
#define bfin_read_IMDMA_D1_START_ADDR (  )     bfin_readPTR(IMDMA_D1_START_ADDR)

 
#define bfin_read_IMDMA_D1_X_COUNT (  )     bfin_read16(IMDMA_D1_X_COUNT)

 
#define bfin_read_IMDMA_D1_X_MODIFY (  )     bfin_read16(IMDMA_D1_X_MODIFY)

 
#define bfin_read_IMDMA_D1_Y_COUNT (  )     bfin_read16(IMDMA_D1_Y_COUNT)

 
#define bfin_read_IMDMA_D1_Y_MODIFY (  )     bfin_read16(IMDMA_D1_Y_MODIFY)

 
#define bfin_read_IMDMA_S0_CONFIG (  )     bfin_read16(IMDMA_S0_CONFIG)

 
#define bfin_read_IMDMA_S0_CURR_ADDR (  )     bfin_readPTR(IMDMA_S0_CURR_ADDR)

 
#define bfin_read_IMDMA_S0_CURR_DESC_PTR (  )     bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)

 
#define bfin_read_IMDMA_S0_CURR_X_COUNT (  )     bfin_read16(IMDMA_S0_CURR_X_COUNT)

 
#define bfin_read_IMDMA_S0_CURR_Y_COUNT (  )     bfin_read16(IMDMA_S0_CURR_Y_COUNT)

 
#define bfin_read_IMDMA_S0_IRQ_STATUS (  )     bfin_read16(IMDMA_S0_IRQ_STATUS)

 
#define bfin_read_IMDMA_S0_NEXT_DESC_PTR (  )     bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)

 
#define bfin_read_IMDMA_S0_START_ADDR (  )     bfin_readPTR(IMDMA_S0_START_ADDR)

 
#define bfin_read_IMDMA_S0_X_COUNT (  )     bfin_read16(IMDMA_S0_X_COUNT)

 
#define bfin_read_IMDMA_S0_X_MODIFY (  )     bfin_read16(IMDMA_S0_X_MODIFY)

 
#define bfin_read_IMDMA_S0_Y_COUNT (  )     bfin_read16(IMDMA_S0_Y_COUNT)

 
#define bfin_read_IMDMA_S0_Y_MODIFY (  )     bfin_read16(IMDMA_S0_Y_MODIFY)

 
#define bfin_read_IMDMA_S1_CONFIG (  )     bfin_read16(IMDMA_S1_CONFIG)

 
#define bfin_read_IMDMA_S1_CURR_ADDR (  )     bfin_readPTR(IMDMA_S1_CURR_ADDR)

 
#define bfin_read_IMDMA_S1_CURR_DESC_PTR (  )     bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)

 
#define bfin_read_IMDMA_S1_CURR_X_COUNT (  )     bfin_read16(IMDMA_S1_CURR_X_COUNT)

 
#define bfin_read_IMDMA_S1_CURR_Y_COUNT (  )     bfin_read16(IMDMA_S1_CURR_Y_COUNT)

 
#define bfin_read_IMDMA_S1_IRQ_STATUS (  )     bfin_read16(IMDMA_S1_IRQ_STATUS)

 
#define bfin_read_IMDMA_S1_NEXT_DESC_PTR (  )     bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)

 
#define bfin_read_IMDMA_S1_START_ADDR (  )     bfin_readPTR(IMDMA_S1_START_ADDR)

 
#define bfin_read_IMDMA_S1_X_COUNT (  )     bfin_read16(IMDMA_S1_X_COUNT)

 
#define bfin_read_IMDMA_S1_X_MODIFY (  )     bfin_read16(IMDMA_S1_X_MODIFY)

 
#define bfin_read_IMDMA_S1_Y_COUNT (  )     bfin_read16(IMDMA_S1_Y_COUNT)

 
#define bfin_read_IMDMA_S1_Y_MODIFY (  )     bfin_read16(IMDMA_S1_Y_MODIFY)

 
#define bfin_read_IPEND (  )     bfin_read32(IPEND)

 
#define bfin_read_IPRIO (  )     bfin_read32(IPRIO)

 
#define bfin_read_MDMA1_D0_CONFIG (  )     bfin_read16(MDMA1_D0_CONFIG)

 
#define bfin_read_MDMA1_D0_CURR_ADDR (  )     bfin_readPTR(MDMA1_D0_CURR_ADDR)

 
#define bfin_read_MDMA1_D0_CURR_DESC_PTR (  )     bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)

 
#define bfin_read_MDMA1_D0_CURR_X_COUNT (  )     bfin_read16(MDMA1_D0_CURR_X_COUNT)

 
#define bfin_read_MDMA1_D0_CURR_Y_COUNT (  )     bfin_read16(MDMA1_D0_CURR_Y_COUNT)

 
#define bfin_read_MDMA1_D0_IRQ_STATUS (  )     bfin_read16(MDMA1_D0_IRQ_STATUS)

 
#define bfin_read_MDMA1_D0_NEXT_DESC_PTR (  )     bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)

 
#define bfin_read_MDMA1_D0_PERIPHERAL_MAP (  )     bfin_read16(MDMA1_D0_PERIPHERAL_MAP)

 
#define bfin_read_MDMA1_D0_START_ADDR (  )     bfin_readPTR(MDMA1_D0_START_ADDR)

 
#define bfin_read_MDMA1_D0_X_COUNT (  )     bfin_read16(MDMA1_D0_X_COUNT)

 
#define bfin_read_MDMA1_D0_X_MODIFY (  )     bfin_read16(MDMA1_D0_X_MODIFY)

 
#define bfin_read_MDMA1_D0_Y_COUNT (  )     bfin_read16(MDMA1_D0_Y_COUNT)

 
#define bfin_read_MDMA1_D0_Y_MODIFY (  )     bfin_read16(MDMA1_D0_Y_MODIFY)

 
#define bfin_read_MDMA1_D1_CONFIG (  )     bfin_read16(MDMA1_D1_CONFIG)

 
#define bfin_read_MDMA1_D1_CURR_ADDR (  )     bfin_readPTR(MDMA1_D1_CURR_ADDR)

 
#define bfin_read_MDMA1_D1_CURR_DESC_PTR (  )     bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)

 
#define bfin_read_MDMA1_D1_CURR_X_COUNT (  )     bfin_read16(MDMA1_D1_CURR_X_COUNT)

 
#define bfin_read_MDMA1_D1_CURR_Y_COUNT (  )     bfin_read16(MDMA1_D1_CURR_Y_COUNT)

 
#define bfin_read_MDMA1_D1_IRQ_STATUS (  )     bfin_read16(MDMA1_D1_IRQ_STATUS)

 
#define bfin_read_MDMA1_D1_NEXT_DESC_PTR (  )     bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)

 
#define bfin_read_MDMA1_D1_PERIPHERAL_MAP (  )     bfin_read16(MDMA1_D1_PERIPHERAL_MAP)

 
#define bfin_read_MDMA1_D1_START_ADDR (  )     bfin_readPTR(MDMA1_D1_START_ADDR)

 
#define bfin_read_MDMA1_D1_X_COUNT (  )     bfin_read16(MDMA1_D1_X_COUNT)

 
#define bfin_read_MDMA1_D1_X_MODIFY (  )     bfin_read16(MDMA1_D1_X_MODIFY)

 
#define bfin_read_MDMA1_D1_Y_COUNT (  )     bfin_read16(MDMA1_D1_Y_COUNT)

 
#define bfin_read_MDMA1_D1_Y_MODIFY (  )     bfin_read16(MDMA1_D1_Y_MODIFY)

 
#define bfin_read_MDMA1_S0_CONFIG (  )     bfin_read16(MDMA1_S0_CONFIG)

 
#define bfin_read_MDMA1_S0_CURR_ADDR (  )     bfin_readPTR(MDMA1_S0_CURR_ADDR)

 
#define bfin_read_MDMA1_S0_CURR_DESC_PTR (  )     bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)

 
#define bfin_read_MDMA1_S0_CURR_X_COUNT (  )     bfin_read16(MDMA1_S0_CURR_X_COUNT)

 
#define bfin_read_MDMA1_S0_CURR_Y_COUNT (  )     bfin_read16(MDMA1_S0_CURR_Y_COUNT)

 
#define bfin_read_MDMA1_S0_IRQ_STATUS (  )     bfin_read16(MDMA1_S0_IRQ_STATUS)

 
#define bfin_read_MDMA1_S0_NEXT_DESC_PTR (  )     bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)

 
#define bfin_read_MDMA1_S0_PERIPHERAL_MAP (  )     bfin_read16(MDMA1_S0_PERIPHERAL_MAP)

 
#define bfin_read_MDMA1_S0_START_ADDR (  )     bfin_readPTR(MDMA1_S0_START_ADDR)

 
#define bfin_read_MDMA1_S0_X_COUNT (  )     bfin_read16(MDMA1_S0_X_COUNT)

 
#define bfin_read_MDMA1_S0_X_MODIFY (  )     bfin_read16(MDMA1_S0_X_MODIFY)

 
#define bfin_read_MDMA1_S0_Y_COUNT (  )     bfin_read16(MDMA1_S0_Y_COUNT)

 
#define bfin_read_MDMA1_S0_Y_MODIFY (  )     bfin_read16(MDMA1_S0_Y_MODIFY)

 
#define bfin_read_MDMA1_S1_CONFIG (  )     bfin_read16(MDMA1_S1_CONFIG)

 
#define bfin_read_MDMA1_S1_CURR_ADDR (  )     bfin_readPTR(MDMA1_S1_CURR_ADDR)

 
#define bfin_read_MDMA1_S1_CURR_DESC_PTR (  )     bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)

 
#define bfin_read_MDMA1_S1_CURR_X_COUNT (  )     bfin_read16(MDMA1_S1_CURR_X_COUNT)

 
#define bfin_read_MDMA1_S1_CURR_Y_COUNT (  )     bfin_read16(MDMA1_S1_CURR_Y_COUNT)

 
#define bfin_read_MDMA1_S1_IRQ_STATUS (  )     bfin_read16(MDMA1_S1_IRQ_STATUS)

 
#define bfin_read_MDMA1_S1_NEXT_DESC_PTR (  )     bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)

 
#define bfin_read_MDMA1_S1_PERIPHERAL_MAP (  )     bfin_read16(MDMA1_S1_PERIPHERAL_MAP)

 
#define bfin_read_MDMA1_S1_START_ADDR (  )     bfin_readPTR(MDMA1_S1_START_ADDR)

 
#define bfin_read_MDMA1_S1_X_COUNT (  )     bfin_read16(MDMA1_S1_X_COUNT)

 
#define bfin_read_MDMA1_S1_X_MODIFY (  )     bfin_read16(MDMA1_S1_X_MODIFY)

 
#define bfin_read_MDMA1_S1_Y_COUNT (  )     bfin_read16(MDMA1_S1_Y_COUNT)

 
#define bfin_read_MDMA1_S1_Y_MODIFY (  )     bfin_read16(MDMA1_S1_Y_MODIFY)

 
#define bfin_read_MDMA2_D0_CONFIG (  )     bfin_read16(MDMA2_D0_CONFIG)

 
#define bfin_read_MDMA2_D0_CURR_ADDR (  )     bfin_readPTR(MDMA2_D0_CURR_ADDR)

 
#define bfin_read_MDMA2_D0_CURR_DESC_PTR (  )     bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)

 
#define bfin_read_MDMA2_D0_CURR_X_COUNT (  )     bfin_read16(MDMA2_D0_CURR_X_COUNT)

 
#define bfin_read_MDMA2_D0_CURR_Y_COUNT (  )     bfin_read16(MDMA2_D0_CURR_Y_COUNT)

 
#define bfin_read_MDMA2_D0_IRQ_STATUS (  )     bfin_read16(MDMA2_D0_IRQ_STATUS)

 
#define bfin_read_MDMA2_D0_NEXT_DESC_PTR (  )     bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)

 
#define bfin_read_MDMA2_D0_PERIPHERAL_MAP (  )     bfin_read16(MDMA2_D0_PERIPHERAL_MAP)

 
#define bfin_read_MDMA2_D0_START_ADDR (  )     bfin_readPTR(MDMA2_D0_START_ADDR)

 
#define bfin_read_MDMA2_D0_X_COUNT (  )     bfin_read16(MDMA2_D0_X_COUNT)

 
#define bfin_read_MDMA2_D0_X_MODIFY (  )     bfin_read16(MDMA2_D0_X_MODIFY)

 
#define bfin_read_MDMA2_D0_Y_COUNT (  )     bfin_read16(MDMA2_D0_Y_COUNT)

 
#define bfin_read_MDMA2_D0_Y_MODIFY (  )     bfin_read16(MDMA2_D0_Y_MODIFY)

 
#define bfin_read_MDMA2_D1_CONFIG (  )     bfin_read16(MDMA2_D1_CONFIG)

 
#define bfin_read_MDMA2_D1_CURR_ADDR (  )     bfin_readPTR(MDMA2_D1_CURR_ADDR)

 
#define bfin_read_MDMA2_D1_CURR_DESC_PTR (  )     bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)

 
#define bfin_read_MDMA2_D1_CURR_X_COUNT (  )     bfin_read16(MDMA2_D1_CURR_X_COUNT)

 
#define bfin_read_MDMA2_D1_CURR_Y_COUNT (  )     bfin_read16(MDMA2_D1_CURR_Y_COUNT)

 
#define bfin_read_MDMA2_D1_IRQ_STATUS (  )     bfin_read16(MDMA2_D1_IRQ_STATUS)

 
#define bfin_read_MDMA2_D1_NEXT_DESC_PTR (  )     bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)

 
#define bfin_read_MDMA2_D1_PERIPHERAL_MAP (  )     bfin_read16(MDMA2_D1_PERIPHERAL_MAP)

 
#define bfin_read_MDMA2_D1_START_ADDR (  )     bfin_readPTR(MDMA2_D1_START_ADDR)

 
#define bfin_read_MDMA2_D1_X_COUNT (  )     bfin_read16(MDMA2_D1_X_COUNT)

 
#define bfin_read_MDMA2_D1_X_MODIFY (  )     bfin_read16(MDMA2_D1_X_MODIFY)

 
#define bfin_read_MDMA2_D1_Y_COUNT (  )     bfin_read16(MDMA2_D1_Y_COUNT)

 
#define bfin_read_MDMA2_D1_Y_MODIFY (  )     bfin_read16(MDMA2_D1_Y_MODIFY)

 
#define bfin_read_MDMA2_S0_CONFIG (  )     bfin_read16(MDMA2_S0_CONFIG)

 
#define bfin_read_MDMA2_S0_CURR_ADDR (  )     bfin_readPTR(MDMA2_S0_CURR_ADDR)

 
#define bfin_read_MDMA2_S0_CURR_DESC_PTR (  )     bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)

 
#define bfin_read_MDMA2_S0_CURR_X_COUNT (  )     bfin_read16(MDMA2_S0_CURR_X_COUNT)

 
#define bfin_read_MDMA2_S0_CURR_Y_COUNT (  )     bfin_read16(MDMA2_S0_CURR_Y_COUNT)

 
#define bfin_read_MDMA2_S0_IRQ_STATUS (  )     bfin_read16(MDMA2_S0_IRQ_STATUS)

 
#define bfin_read_MDMA2_S0_NEXT_DESC_PTR (  )     bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)

 
#define bfin_read_MDMA2_S0_PERIPHERAL_MAP (  )     bfin_read16(MDMA2_S0_PERIPHERAL_MAP)

 
#define bfin_read_MDMA2_S0_START_ADDR (  )     bfin_readPTR(MDMA2_S0_START_ADDR)

 
#define bfin_read_MDMA2_S0_X_COUNT (  )     bfin_read16(MDMA2_S0_X_COUNT)

 
#define bfin_read_MDMA2_S0_X_MODIFY (  )     bfin_read16(MDMA2_S0_X_MODIFY)

 
#define bfin_read_MDMA2_S0_Y_COUNT (  )     bfin_read16(MDMA2_S0_Y_COUNT)

 
#define bfin_read_MDMA2_S0_Y_MODIFY (  )     bfin_read16(MDMA2_S0_Y_MODIFY)

 
#define bfin_read_MDMA2_S1_CONFIG (  )     bfin_read16(MDMA2_S1_CONFIG)

 
#define bfin_read_MDMA2_S1_CURR_ADDR (  )     bfin_readPTR(MDMA2_S1_CURR_ADDR)

 
#define bfin_read_MDMA2_S1_CURR_DESC_PTR (  )     bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)

 
#define bfin_read_MDMA2_S1_CURR_X_COUNT (  )     bfin_read16(MDMA2_S1_CURR_X_COUNT)

 
#define bfin_read_MDMA2_S1_CURR_Y_COUNT (  )     bfin_read16(MDMA2_S1_CURR_Y_COUNT)

 
#define bfin_read_MDMA2_S1_IRQ_STATUS (  )     bfin_read16(MDMA2_S1_IRQ_STATUS)

 
#define bfin_read_MDMA2_S1_NEXT_DESC_PTR (  )     bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)

 
#define bfin_read_MDMA2_S1_PERIPHERAL_MAP (  )     bfin_read16(MDMA2_S1_PERIPHERAL_MAP)

 
#define bfin_read_MDMA2_S1_START_ADDR (  )     bfin_readPTR(MDMA2_S1_START_ADDR)

 
#define bfin_read_MDMA2_S1_X_COUNT (  )     bfin_read16(MDMA2_S1_X_COUNT)

 
#define bfin_read_MDMA2_S1_X_MODIFY (  )     bfin_read16(MDMA2_S1_X_MODIFY)

 
#define bfin_read_MDMA2_S1_Y_COUNT (  )     bfin_read16(MDMA2_S1_Y_COUNT)

 
#define bfin_read_MDMA2_S1_Y_MODIFY (  )     bfin_read16(MDMA2_S1_Y_MODIFY)

 
#define bfin_read_PLL_CTL (  )     bfin_read16(PLL_CTL)

 
#define bfin_read_PLL_DIV (  )     bfin_read16(PLL_DIV)

 
#define bfin_read_PLL_LOCKCNT (  )     bfin_read16(PLL_LOCKCNT)

 
#define bfin_read_PLL_STAT (  )     bfin_read16(PLL_STAT)

 
#define bfin_read_SPI_BAUD (  )     bfin_read16(SPI_BAUD)

 
#define bfin_read_SPI_CTL (  )     bfin_read16(SPI_CTL)

 
#define bfin_read_SPI_FLG (  )     bfin_read16(SPI_FLG)

 
#define bfin_read_SPI_RDBR (  )     bfin_read16(SPI_RDBR)

 
#define bfin_read_SPI_SHADOW (  )     bfin_read16(SPI_SHADOW)

 
#define bfin_read_SPI_STAT (  )     bfin_read16(SPI_STAT)

 
#define bfin_read_SPI_TDBR (  )     bfin_read16(SPI_TDBR)

 
#define bfin_read_SPORT0_CHNL (  )     bfin_read16(SPORT0_CHNL)

 
#define bfin_read_SPORT0_MCMC1 (  )     bfin_read16(SPORT0_MCMC1)

 
#define bfin_read_SPORT0_MCMC2 (  )     bfin_read16(SPORT0_MCMC2)

 
#define bfin_read_SPORT0_MRCS0 (  )     bfin_read32(SPORT0_MRCS0)

 
#define bfin_read_SPORT0_MRCS1 (  )     bfin_read32(SPORT0_MRCS1)

 
#define bfin_read_SPORT0_MRCS2 (  )     bfin_read32(SPORT0_MRCS2)

 
#define bfin_read_SPORT0_MRCS3 (  )     bfin_read32(SPORT0_MRCS3)

 
#define bfin_read_SPORT0_MTCS0 (  )     bfin_read32(SPORT0_MTCS0)

 
#define bfin_read_SPORT0_MTCS1 (  )     bfin_read32(SPORT0_MTCS1)

 
#define bfin_read_SPORT0_MTCS2 (  )     bfin_read32(SPORT0_MTCS2)

 
#define bfin_read_SPORT0_MTCS3 (  )     bfin_read32(SPORT0_MTCS3)

 
#define bfin_read_SPORT0_RCLKDIV (  )     bfin_read16(SPORT0_RCLKDIV)

 
#define bfin_read_SPORT0_RCR1 (  )     bfin_read16(SPORT0_RCR1)

 
#define bfin_read_SPORT0_RCR2 (  )     bfin_read16(SPORT0_RCR2)

 
#define bfin_read_SPORT0_RFSDIV (  )     bfin_read16(SPORT0_RFSDIV)

 
#define bfin_read_SPORT0_RX (  )     bfin_read32(SPORT0_RX)

 
#define bfin_read_SPORT0_STAT (  )     bfin_read16(SPORT0_STAT)

 
#define bfin_read_SPORT0_TCLKDIV (  )     bfin_read16(SPORT0_TCLKDIV)

 
#define bfin_read_SPORT0_TCR1 (  )     bfin_read16(SPORT0_TCR1)

 
#define bfin_read_SPORT0_TCR2 (  )     bfin_read16(SPORT0_TCR2)

 
#define bfin_read_SPORT0_TFSDIV (  )     bfin_read16(SPORT0_TFSDIV)

 
#define bfin_read_SPORT0_TX (  )     bfin_read32(SPORT0_TX)

 
#define bfin_read_SPORT1_CHNL (  )     bfin_read16(SPORT1_CHNL)

 
#define bfin_read_SPORT1_MCMC1 (  )     bfin_read16(SPORT1_MCMC1)

 
#define bfin_read_SPORT1_MCMC2 (  )     bfin_read16(SPORT1_MCMC2)

 
#define bfin_read_SPORT1_MRCS0 (  )     bfin_read32(SPORT1_MRCS0)

 
#define bfin_read_SPORT1_MRCS1 (  )     bfin_read32(SPORT1_MRCS1)

 
#define bfin_read_SPORT1_MRCS2 (  )     bfin_read32(SPORT1_MRCS2)

 
#define bfin_read_SPORT1_MRCS3 (  )     bfin_read32(SPORT1_MRCS3)

 
#define bfin_read_SPORT1_MTCS0 (  )     bfin_read32(SPORT1_MTCS0)

 
#define bfin_read_SPORT1_MTCS1 (  )     bfin_read32(SPORT1_MTCS1)

 
#define bfin_read_SPORT1_MTCS2 (  )     bfin_read32(SPORT1_MTCS2)

 
#define bfin_read_SPORT1_MTCS3 (  )     bfin_read32(SPORT1_MTCS3)

 
#define bfin_read_SPORT1_RCLKDIV (  )     bfin_read16(SPORT1_RCLKDIV)

 
#define bfin_read_SPORT1_RCR1 (  )     bfin_read16(SPORT1_RCR1)

 
#define bfin_read_SPORT1_RCR2 (  )     bfin_read16(SPORT1_RCR2)

 
#define bfin_read_SPORT1_RFSDIV (  )     bfin_read16(SPORT1_RFSDIV)

 
#define bfin_read_SPORT1_RX (  )     bfin_read32(SPORT1_RX)

 
#define bfin_read_SPORT1_STAT (  )     bfin_read16(SPORT1_STAT)

 
#define bfin_read_SPORT1_TCLKDIV (  )     bfin_read16(SPORT1_TCLKDIV)

 
#define bfin_read_SPORT1_TCR1 (  )     bfin_read16(SPORT1_TCR1)

 
#define bfin_read_SPORT1_TCR2 (  )     bfin_read16(SPORT1_TCR2)

 
#define bfin_read_SPORT1_TFSDIV (  )     bfin_read16(SPORT1_TFSDIV)

 
#define bfin_read_SPORT1_TX (  )     bfin_read32(SPORT1_TX)

 
#define bfin_read_TCNTL (  )     bfin_read32(TCNTL)

 
#define bfin_read_TCOUNT (  )     bfin_read32(TCOUNT)

 
#define bfin_read_TIMER0_CONFIG (  )     bfin_read16(TIMER0_CONFIG)

 
#define bfin_read_TIMER0_COUNTER (  )     bfin_read32(TIMER0_COUNTER)

 
#define bfin_read_TIMER0_PERIOD (  )     bfin_read32(TIMER0_PERIOD)

 
#define bfin_read_TIMER0_WIDTH (  )     bfin_read32(TIMER0_WIDTH)

 
#define bfin_read_TIMER10_CONFIG (  )     bfin_read16(TIMER10_CONFIG)

 
#define bfin_read_TIMER10_COUNTER (  )     bfin_read32(TIMER10_COUNTER)

 
#define bfin_read_TIMER10_PERIOD (  )     bfin_read32(TIMER10_PERIOD)

 
#define bfin_read_TIMER10_WIDTH (  )     bfin_read32(TIMER10_WIDTH)

 
#define bfin_read_TIMER11_CONFIG (  )     bfin_read16(TIMER11_CONFIG)

 
#define bfin_read_TIMER11_COUNTER (  )     bfin_read32(TIMER11_COUNTER)

 
#define bfin_read_TIMER11_PERIOD (  )     bfin_read32(TIMER11_PERIOD)

 
#define bfin_read_TIMER11_WIDTH (  )     bfin_read32(TIMER11_WIDTH)

 
#define bfin_read_TIMER1_CONFIG (  )     bfin_read16(TIMER1_CONFIG)

 
#define bfin_read_TIMER1_COUNTER (  )     bfin_read32(TIMER1_COUNTER)

 
#define bfin_read_TIMER1_PERIOD (  )     bfin_read32(TIMER1_PERIOD)

 
#define bfin_read_TIMER1_WIDTH (  )     bfin_read32(TIMER1_WIDTH)

 
#define bfin_read_TIMER2_CONFIG (  )     bfin_read16(TIMER2_CONFIG)

 
#define bfin_read_TIMER2_COUNTER (  )     bfin_read32(TIMER2_COUNTER)

 
#define bfin_read_TIMER2_PERIOD (  )     bfin_read32(TIMER2_PERIOD)

 
#define bfin_read_TIMER2_WIDTH (  )     bfin_read32(TIMER2_WIDTH)

 
#define bfin_read_TIMER3_CONFIG (  )     bfin_read16(TIMER3_CONFIG)

 
#define bfin_read_TIMER3_COUNTER (  )     bfin_read32(TIMER3_COUNTER)

 
#define bfin_read_TIMER3_PERIOD (  )     bfin_read32(TIMER3_PERIOD)

 
#define bfin_read_TIMER3_WIDTH (  )     bfin_read32(TIMER3_WIDTH)

 
#define bfin_read_TIMER4_CONFIG (  )     bfin_read16(TIMER4_CONFIG)

 
#define bfin_read_TIMER4_COUNTER (  )     bfin_read32(TIMER4_COUNTER)

 
#define bfin_read_TIMER4_PERIOD (  )     bfin_read32(TIMER4_PERIOD)

 
#define bfin_read_TIMER4_WIDTH (  )     bfin_read32(TIMER4_WIDTH)

 
#define bfin_read_TIMER5_CONFIG (  )     bfin_read16(TIMER5_CONFIG)

 
#define bfin_read_TIMER5_COUNTER (  )     bfin_read32(TIMER5_COUNTER)

 
#define bfin_read_TIMER5_PERIOD (  )     bfin_read32(TIMER5_PERIOD)

 
#define bfin_read_TIMER5_WIDTH (  )     bfin_read32(TIMER5_WIDTH)

 
#define bfin_read_TIMER6_CONFIG (  )     bfin_read16(TIMER6_CONFIG)

 
#define bfin_read_TIMER6_COUNTER (  )     bfin_read32(TIMER6_COUNTER)

 
#define bfin_read_TIMER6_PERIOD (  )     bfin_read32(TIMER6_PERIOD)

 
#define bfin_read_TIMER6_WIDTH (  )     bfin_read32(TIMER6_WIDTH)

 
#define bfin_read_TIMER7_CONFIG (  )     bfin_read16(TIMER7_CONFIG)

 
#define bfin_read_TIMER7_COUNTER (  )     bfin_read32(TIMER7_COUNTER)

 
#define bfin_read_TIMER7_PERIOD (  )     bfin_read32(TIMER7_PERIOD)

 
#define bfin_read_TIMER7_WIDTH (  )     bfin_read32(TIMER7_WIDTH)

 
#define bfin_read_TIMER8_CONFIG (  )     bfin_read16(TIMER8_CONFIG)

 
#define bfin_read_TIMER8_COUNTER (  )     bfin_read32(TIMER8_COUNTER)

 
#define bfin_read_TIMER8_PERIOD (  )     bfin_read32(TIMER8_PERIOD)

 
#define bfin_read_TIMER8_WIDTH (  )     bfin_read32(TIMER8_WIDTH)

 
#define bfin_read_TIMER9_CONFIG (  )     bfin_read16(TIMER9_CONFIG)

 
#define bfin_read_TIMER9_COUNTER (  )     bfin_read32(TIMER9_COUNTER)

 
#define bfin_read_TIMER9_PERIOD (  )     bfin_read32(TIMER9_PERIOD)

 
#define bfin_read_TIMER9_WIDTH (  )     bfin_read32(TIMER9_WIDTH)

 
#define bfin_read_TMRS4_DISABLE (  )     bfin_read32(TMRS4_DISABLE)

 
#define bfin_read_TMRS4_ENABLE (  )     bfin_read32(TMRS4_ENABLE)

 
#define bfin_read_TMRS4_STATUS (  )     bfin_read32(TMRS4_STATUS)

 
#define bfin_read_TMRS8_DISABLE (  )     bfin_read32(TMRS8_DISABLE)

 
#define bfin_read_TMRS8_ENABLE (  )     bfin_read32(TMRS8_ENABLE)

 
#define bfin_read_TMRS8_STATUS (  )     bfin_read32(TMRS8_STATUS)

 
#define bfin_read_TPERIOD (  )     bfin_read32(TPERIOD)

 
#define bfin_read_TSCALE (  )     bfin_read32(TSCALE)

 
#define bfin_read_VR_CTL (  )     bfin_read16(VR_CTL)

 
#define bfin_read_WDOGA_CNT (  )     bfin_read32(WDOGA_CNT)

 
#define bfin_read_WDOGA_CTL (  )     bfin_read16(WDOGA_CTL)

 
#define bfin_read_WDOGA_STAT (  )     bfin_read32(WDOGA_STAT)

 
#define bfin_read_WDOGB_CNT (  )     bfin_read32(WDOGB_CNT)

 
#define bfin_read_WDOGB_CTL (  )     bfin_read16(WDOGB_CTL)

 
#define bfin_read_WDOGB_STAT (  )     bfin_read32(WDOGB_STAT)

#define bfin_write_CHIPID ( val   )     bfin_write32(CHIPID, val)

#define bfin_write_DMA1_0_CONFIG ( val   )     bfin_write16(DMA1_0_CONFIG, val)

#define bfin_write_DMA1_0_CURR_ADDR ( val   )     bfin_writePTR(DMA1_0_CURR_ADDR, val)

#define bfin_write_DMA1_0_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)

#define bfin_write_DMA1_0_CURR_X_COUNT ( val   )     bfin_write16(DMA1_0_CURR_X_COUNT, val)

#define bfin_write_DMA1_0_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_0_CURR_Y_COUNT, val)

#define bfin_write_DMA1_0_IRQ_STATUS ( val   )     bfin_write16(DMA1_0_IRQ_STATUS, val)

#define bfin_write_DMA1_0_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_0_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_0_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_0_START_ADDR ( val   )     bfin_writePTR(DMA1_0_START_ADDR, val)

#define bfin_write_DMA1_0_X_COUNT ( val   )     bfin_write16(DMA1_0_X_COUNT, val)

#define bfin_write_DMA1_0_X_MODIFY ( val   )     bfin_write16(DMA1_0_X_MODIFY, val)

#define bfin_write_DMA1_0_Y_COUNT ( val   )     bfin_write16(DMA1_0_Y_COUNT, val)

#define bfin_write_DMA1_0_Y_MODIFY ( val   )     bfin_write16(DMA1_0_Y_MODIFY, val)

#define bfin_write_DMA1_10_CONFIG ( val   )     bfin_write16(DMA1_10_CONFIG, val)

#define bfin_write_DMA1_10_CURR_ADDR ( val   )     bfin_writePTR(DMA1_10_CURR_ADDR, val)

#define bfin_write_DMA1_10_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)

#define bfin_write_DMA1_10_CURR_X_COUNT ( val   )     bfin_write16(DMA1_10_CURR_X_COUNT, val)

#define bfin_write_DMA1_10_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_10_CURR_Y_COUNT, val)

#define bfin_write_DMA1_10_IRQ_STATUS ( val   )     bfin_write16(DMA1_10_IRQ_STATUS, val)

#define bfin_write_DMA1_10_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_10_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_10_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_10_START_ADDR ( val   )     bfin_writePTR(DMA1_10_START_ADDR, val)

#define bfin_write_DMA1_10_X_COUNT ( val   )     bfin_write16(DMA1_10_X_COUNT, val)

#define bfin_write_DMA1_10_X_MODIFY ( val   )     bfin_write16(DMA1_10_X_MODIFY, val)

#define bfin_write_DMA1_10_Y_COUNT ( val   )     bfin_write16(DMA1_10_Y_COUNT, val)

#define bfin_write_DMA1_10_Y_MODIFY ( val   )     bfin_write16(DMA1_10_Y_MODIFY, val)

#define bfin_write_DMA1_11_CONFIG ( val   )     bfin_write16(DMA1_11_CONFIG, val)

#define bfin_write_DMA1_11_CURR_ADDR ( val   )     bfin_writePTR(DMA1_11_CURR_ADDR, val)

#define bfin_write_DMA1_11_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)

#define bfin_write_DMA1_11_CURR_X_COUNT ( val   )     bfin_write16(DMA1_11_CURR_X_COUNT, val)

#define bfin_write_DMA1_11_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_11_CURR_Y_COUNT, val)

#define bfin_write_DMA1_11_IRQ_STATUS ( val   )     bfin_write16(DMA1_11_IRQ_STATUS, val)

#define bfin_write_DMA1_11_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_11_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_11_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_11_START_ADDR ( val   )     bfin_writePTR(DMA1_11_START_ADDR, val)

#define bfin_write_DMA1_11_X_COUNT ( val   )     bfin_write16(DMA1_11_X_COUNT, val)

#define bfin_write_DMA1_11_X_MODIFY ( val   )     bfin_write16(DMA1_11_X_MODIFY, val)

#define bfin_write_DMA1_11_Y_COUNT ( val   )     bfin_write16(DMA1_11_Y_COUNT, val)

#define bfin_write_DMA1_11_Y_MODIFY ( val   )     bfin_write16(DMA1_11_Y_MODIFY, val)

#define bfin_write_DMA1_1_CONFIG ( val   )     bfin_write16(DMA1_1_CONFIG, val)

#define bfin_write_DMA1_1_CURR_ADDR ( val   )     bfin_writePTR(DMA1_1_CURR_ADDR, val)

#define bfin_write_DMA1_1_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)

#define bfin_write_DMA1_1_CURR_X_COUNT ( val   )     bfin_write16(DMA1_1_CURR_X_COUNT, val)

#define bfin_write_DMA1_1_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_1_CURR_Y_COUNT, val)

#define bfin_write_DMA1_1_IRQ_STATUS ( val   )     bfin_write16(DMA1_1_IRQ_STATUS, val)

#define bfin_write_DMA1_1_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_1_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_1_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_1_START_ADDR ( val   )     bfin_writePTR(DMA1_1_START_ADDR, val)

#define bfin_write_DMA1_1_X_COUNT ( val   )     bfin_write16(DMA1_1_X_COUNT, val)

#define bfin_write_DMA1_1_X_MODIFY ( val   )     bfin_write16(DMA1_1_X_MODIFY, val)

#define bfin_write_DMA1_1_Y_COUNT ( val   )     bfin_write16(DMA1_1_Y_COUNT, val)

#define bfin_write_DMA1_1_Y_MODIFY ( val   )     bfin_write16(DMA1_1_Y_MODIFY, val)

#define bfin_write_DMA1_2_CONFIG ( val   )     bfin_write16(DMA1_2_CONFIG, val)

#define bfin_write_DMA1_2_CURR_ADDR ( val   )     bfin_writePTR(DMA1_2_CURR_ADDR, val)

#define bfin_write_DMA1_2_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)

#define bfin_write_DMA1_2_CURR_X_COUNT ( val   )     bfin_write16(DMA1_2_CURR_X_COUNT, val)

#define bfin_write_DMA1_2_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_2_CURR_Y_COUNT, val)

#define bfin_write_DMA1_2_IRQ_STATUS ( val   )     bfin_write16(DMA1_2_IRQ_STATUS, val)

#define bfin_write_DMA1_2_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_2_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_2_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_2_START_ADDR ( val   )     bfin_writePTR(DMA1_2_START_ADDR, val)

#define bfin_write_DMA1_2_X_COUNT ( val   )     bfin_write16(DMA1_2_X_COUNT, val)

#define bfin_write_DMA1_2_X_MODIFY ( val   )     bfin_write16(DMA1_2_X_MODIFY, val)

#define bfin_write_DMA1_2_Y_COUNT ( val   )     bfin_write16(DMA1_2_Y_COUNT, val)

#define bfin_write_DMA1_2_Y_MODIFY ( val   )     bfin_write16(DMA1_2_Y_MODIFY, val)

#define bfin_write_DMA1_3_CONFIG ( val   )     bfin_write16(DMA1_3_CONFIG, val)

#define bfin_write_DMA1_3_CURR_ADDR ( val   )     bfin_writePTR(DMA1_3_CURR_ADDR, val)

#define bfin_write_DMA1_3_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)

#define bfin_write_DMA1_3_CURR_X_COUNT ( val   )     bfin_write16(DMA1_3_CURR_X_COUNT, val)

#define bfin_write_DMA1_3_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_3_CURR_Y_COUNT, val)

#define bfin_write_DMA1_3_IRQ_STATUS ( val   )     bfin_write16(DMA1_3_IRQ_STATUS, val)

#define bfin_write_DMA1_3_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_3_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_3_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_3_START_ADDR ( val   )     bfin_writePTR(DMA1_3_START_ADDR, val)

#define bfin_write_DMA1_3_X_COUNT ( val   )     bfin_write16(DMA1_3_X_COUNT, val)

#define bfin_write_DMA1_3_X_MODIFY ( val   )     bfin_write16(DMA1_3_X_MODIFY, val)

#define bfin_write_DMA1_3_Y_COUNT ( val   )     bfin_write16(DMA1_3_Y_COUNT, val)

#define bfin_write_DMA1_3_Y_MODIFY ( val   )     bfin_write16(DMA1_3_Y_MODIFY, val)

#define bfin_write_DMA1_4_CONFIG ( val   )     bfin_write16(DMA1_4_CONFIG, val)

#define bfin_write_DMA1_4_CURR_ADDR ( val   )     bfin_writePTR(DMA1_4_CURR_ADDR, val)

#define bfin_write_DMA1_4_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)

#define bfin_write_DMA1_4_CURR_X_COUNT ( val   )     bfin_write16(DMA1_4_CURR_X_COUNT, val)

#define bfin_write_DMA1_4_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_4_CURR_Y_COUNT, val)

#define bfin_write_DMA1_4_IRQ_STATUS ( val   )     bfin_write16(DMA1_4_IRQ_STATUS, val)

#define bfin_write_DMA1_4_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_4_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_4_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_4_START_ADDR ( val   )     bfin_writePTR(DMA1_4_START_ADDR, val)

#define bfin_write_DMA1_4_X_COUNT ( val   )     bfin_write16(DMA1_4_X_COUNT, val)

#define bfin_write_DMA1_4_X_MODIFY ( val   )     bfin_write16(DMA1_4_X_MODIFY, val)

#define bfin_write_DMA1_4_Y_COUNT ( val   )     bfin_write16(DMA1_4_Y_COUNT, val)

#define bfin_write_DMA1_4_Y_MODIFY ( val   )     bfin_write16(DMA1_4_Y_MODIFY, val)

#define bfin_write_DMA1_5_CONFIG ( val   )     bfin_write16(DMA1_5_CONFIG, val)

#define bfin_write_DMA1_5_CURR_ADDR ( val   )     bfin_writePTR(DMA1_5_CURR_ADDR, val)

#define bfin_write_DMA1_5_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)

#define bfin_write_DMA1_5_CURR_X_COUNT ( val   )     bfin_write16(DMA1_5_CURR_X_COUNT, val)

#define bfin_write_DMA1_5_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_5_CURR_Y_COUNT, val)

#define bfin_write_DMA1_5_IRQ_STATUS ( val   )     bfin_write16(DMA1_5_IRQ_STATUS, val)

#define bfin_write_DMA1_5_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_5_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_5_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_5_START_ADDR ( val   )     bfin_writePTR(DMA1_5_START_ADDR, val)

#define bfin_write_DMA1_5_X_COUNT ( val   )     bfin_write16(DMA1_5_X_COUNT, val)

#define bfin_write_DMA1_5_X_MODIFY ( val   )     bfin_write16(DMA1_5_X_MODIFY, val)

#define bfin_write_DMA1_5_Y_COUNT ( val   )     bfin_write16(DMA1_5_Y_COUNT, val)

#define bfin_write_DMA1_5_Y_MODIFY ( val   )     bfin_write16(DMA1_5_Y_MODIFY, val)

#define bfin_write_DMA1_6_CONFIG ( val   )     bfin_write16(DMA1_6_CONFIG, val)

#define bfin_write_DMA1_6_CURR_ADDR ( val   )     bfin_writePTR(DMA1_6_CURR_ADDR, val)

#define bfin_write_DMA1_6_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)

#define bfin_write_DMA1_6_CURR_X_COUNT ( val   )     bfin_write16(DMA1_6_CURR_X_COUNT, val)

#define bfin_write_DMA1_6_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_6_CURR_Y_COUNT, val)

#define bfin_write_DMA1_6_IRQ_STATUS ( val   )     bfin_write16(DMA1_6_IRQ_STATUS, val)

#define bfin_write_DMA1_6_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_6_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_6_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_6_START_ADDR ( val   )     bfin_writePTR(DMA1_6_START_ADDR, val)

#define bfin_write_DMA1_6_X_COUNT ( val   )     bfin_write16(DMA1_6_X_COUNT, val)

#define bfin_write_DMA1_6_X_MODIFY ( val   )     bfin_write16(DMA1_6_X_MODIFY, val)

#define bfin_write_DMA1_6_Y_COUNT ( val   )     bfin_write16(DMA1_6_Y_COUNT, val)

#define bfin_write_DMA1_6_Y_MODIFY ( val   )     bfin_write16(DMA1_6_Y_MODIFY, val)

#define bfin_write_DMA1_7_CONFIG ( val   )     bfin_write16(DMA1_7_CONFIG, val)

#define bfin_write_DMA1_7_CURR_ADDR ( val   )     bfin_writePTR(DMA1_7_CURR_ADDR, val)

#define bfin_write_DMA1_7_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)

#define bfin_write_DMA1_7_CURR_X_COUNT ( val   )     bfin_write16(DMA1_7_CURR_X_COUNT, val)

#define bfin_write_DMA1_7_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_7_CURR_Y_COUNT, val)

#define bfin_write_DMA1_7_IRQ_STATUS ( val   )     bfin_write16(DMA1_7_IRQ_STATUS, val)

#define bfin_write_DMA1_7_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_7_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_7_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_7_START_ADDR ( val   )     bfin_writePTR(DMA1_7_START_ADDR, val)

#define bfin_write_DMA1_7_X_COUNT ( val   )     bfin_write16(DMA1_7_X_COUNT, val)

#define bfin_write_DMA1_7_X_MODIFY ( val   )     bfin_write16(DMA1_7_X_MODIFY, val)

#define bfin_write_DMA1_7_Y_COUNT ( val   )     bfin_write16(DMA1_7_Y_COUNT, val)

#define bfin_write_DMA1_7_Y_MODIFY ( val   )     bfin_write16(DMA1_7_Y_MODIFY, val)

#define bfin_write_DMA1_8_CONFIG ( val   )     bfin_write16(DMA1_8_CONFIG, val)

#define bfin_write_DMA1_8_CURR_ADDR ( val   )     bfin_writePTR(DMA1_8_CURR_ADDR, val)

#define bfin_write_DMA1_8_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)

#define bfin_write_DMA1_8_CURR_X_COUNT ( val   )     bfin_write16(DMA1_8_CURR_X_COUNT, val)

#define bfin_write_DMA1_8_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_8_CURR_Y_COUNT, val)

#define bfin_write_DMA1_8_IRQ_STATUS ( val   )     bfin_write16(DMA1_8_IRQ_STATUS, val)

#define bfin_write_DMA1_8_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_8_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_8_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_8_START_ADDR ( val   )     bfin_writePTR(DMA1_8_START_ADDR, val)

#define bfin_write_DMA1_8_X_COUNT ( val   )     bfin_write16(DMA1_8_X_COUNT, val)

#define bfin_write_DMA1_8_X_MODIFY ( val   )     bfin_write16(DMA1_8_X_MODIFY, val)

#define bfin_write_DMA1_8_Y_COUNT ( val   )     bfin_write16(DMA1_8_Y_COUNT, val)

#define bfin_write_DMA1_8_Y_MODIFY ( val   )     bfin_write16(DMA1_8_Y_MODIFY, val)

#define bfin_write_DMA1_9_CONFIG ( val   )     bfin_write16(DMA1_9_CONFIG, val)

#define bfin_write_DMA1_9_CURR_ADDR ( val   )     bfin_writePTR(DMA1_9_CURR_ADDR, val)

#define bfin_write_DMA1_9_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)

#define bfin_write_DMA1_9_CURR_X_COUNT ( val   )     bfin_write16(DMA1_9_CURR_X_COUNT, val)

#define bfin_write_DMA1_9_CURR_Y_COUNT ( val   )     bfin_write16(DMA1_9_CURR_Y_COUNT, val)

#define bfin_write_DMA1_9_IRQ_STATUS ( val   )     bfin_write16(DMA1_9_IRQ_STATUS, val)

#define bfin_write_DMA1_9_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)

#define bfin_write_DMA1_9_PERIPHERAL_MAP ( val   )     bfin_write16(DMA1_9_PERIPHERAL_MAP, val)

#define bfin_write_DMA1_9_START_ADDR ( val   )     bfin_writePTR(DMA1_9_START_ADDR, val)

#define bfin_write_DMA1_9_X_COUNT ( val   )     bfin_write16(DMA1_9_X_COUNT, val)

#define bfin_write_DMA1_9_X_MODIFY ( val   )     bfin_write16(DMA1_9_X_MODIFY, val)

#define bfin_write_DMA1_9_Y_COUNT ( val   )     bfin_write16(DMA1_9_Y_COUNT, val)

#define bfin_write_DMA1_9_Y_MODIFY ( val   )     bfin_write16(DMA1_9_Y_MODIFY, val)

#define bfin_write_DMA1_TC_CNT ( val   )     bfin_write16(DMA1_TC_CNT, val)

#define bfin_write_DMA1_TC_PER ( val   )     bfin_write16(DMA1_TC_PER, val)

#define bfin_write_DMA2_0_CONFIG ( val   )     bfin_write16(DMA2_0_CONFIG, val)

#define bfin_write_DMA2_0_CURR_ADDR ( val   )     bfin_writePTR(DMA2_0_CURR_ADDR, val)

#define bfin_write_DMA2_0_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)

#define bfin_write_DMA2_0_CURR_X_COUNT ( val   )     bfin_write16(DMA2_0_CURR_X_COUNT, val)

#define bfin_write_DMA2_0_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_0_CURR_Y_COUNT, val)

#define bfin_write_DMA2_0_IRQ_STATUS ( val   )     bfin_write16(DMA2_0_IRQ_STATUS, val)

#define bfin_write_DMA2_0_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_0_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_0_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_0_START_ADDR ( val   )     bfin_writePTR(DMA2_0_START_ADDR, val)

#define bfin_write_DMA2_0_X_COUNT ( val   )     bfin_write16(DMA2_0_X_COUNT, val)

#define bfin_write_DMA2_0_X_MODIFY ( val   )     bfin_write16(DMA2_0_X_MODIFY, val)

#define bfin_write_DMA2_0_Y_COUNT ( val   )     bfin_write16(DMA2_0_Y_COUNT, val)

#define bfin_write_DMA2_0_Y_MODIFY ( val   )     bfin_write16(DMA2_0_Y_MODIFY, val)

#define bfin_write_DMA2_10_CONFIG ( val   )     bfin_write16(DMA2_10_CONFIG, val)

#define bfin_write_DMA2_10_CURR_ADDR ( val   )     bfin_writePTR(DMA2_10_CURR_ADDR, val)

#define bfin_write_DMA2_10_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)

#define bfin_write_DMA2_10_CURR_X_COUNT ( val   )     bfin_write16(DMA2_10_CURR_X_COUNT, val)

#define bfin_write_DMA2_10_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_10_CURR_Y_COUNT, val)

#define bfin_write_DMA2_10_IRQ_STATUS ( val   )     bfin_write16(DMA2_10_IRQ_STATUS, val)

#define bfin_write_DMA2_10_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_10_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_10_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_10_START_ADDR ( val   )     bfin_writePTR(DMA2_10_START_ADDR, val)

#define bfin_write_DMA2_10_X_COUNT ( val   )     bfin_write16(DMA2_10_X_COUNT, val)

#define bfin_write_DMA2_10_X_MODIFY ( val   )     bfin_write16(DMA2_10_X_MODIFY, val)

#define bfin_write_DMA2_10_Y_COUNT ( val   )     bfin_write16(DMA2_10_Y_COUNT, val)

#define bfin_write_DMA2_10_Y_MODIFY ( val   )     bfin_write16(DMA2_10_Y_MODIFY, val)

#define bfin_write_DMA2_11_CONFIG ( val   )     bfin_write16(DMA2_11_CONFIG, val)

#define bfin_write_DMA2_11_CURR_ADDR ( val   )     bfin_writePTR(DMA2_11_CURR_ADDR, val)

#define bfin_write_DMA2_11_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)

#define bfin_write_DMA2_11_CURR_X_COUNT ( val   )     bfin_write16(DMA2_11_CURR_X_COUNT, val)

#define bfin_write_DMA2_11_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_11_CURR_Y_COUNT, val)

#define bfin_write_DMA2_11_IRQ_STATUS ( val   )     bfin_write16(DMA2_11_IRQ_STATUS, val)

#define bfin_write_DMA2_11_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_11_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_11_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_11_START_ADDR ( val   )     bfin_writePTR(DMA2_11_START_ADDR, val)

#define bfin_write_DMA2_11_X_COUNT ( val   )     bfin_write16(DMA2_11_X_COUNT, val)

#define bfin_write_DMA2_11_X_MODIFY ( val   )     bfin_write16(DMA2_11_X_MODIFY, val)

#define bfin_write_DMA2_11_Y_COUNT ( val   )     bfin_write16(DMA2_11_Y_COUNT, val)

#define bfin_write_DMA2_11_Y_MODIFY ( val   )     bfin_write16(DMA2_11_Y_MODIFY, val)

#define bfin_write_DMA2_1_CONFIG ( val   )     bfin_write16(DMA2_1_CONFIG, val)

#define bfin_write_DMA2_1_CURR_ADDR ( val   )     bfin_writePTR(DMA2_1_CURR_ADDR, val)

#define bfin_write_DMA2_1_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)

#define bfin_write_DMA2_1_CURR_X_COUNT ( val   )     bfin_write16(DMA2_1_CURR_X_COUNT, val)

#define bfin_write_DMA2_1_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_1_CURR_Y_COUNT, val)

#define bfin_write_DMA2_1_IRQ_STATUS ( val   )     bfin_write16(DMA2_1_IRQ_STATUS, val)

#define bfin_write_DMA2_1_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_1_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_1_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_1_START_ADDR ( val   )     bfin_writePTR(DMA2_1_START_ADDR, val)

#define bfin_write_DMA2_1_X_COUNT ( val   )     bfin_write16(DMA2_1_X_COUNT, val)

#define bfin_write_DMA2_1_X_MODIFY ( val   )     bfin_write16(DMA2_1_X_MODIFY, val)

#define bfin_write_DMA2_1_Y_COUNT ( val   )     bfin_write16(DMA2_1_Y_COUNT, val)

#define bfin_write_DMA2_1_Y_MODIFY ( val   )     bfin_write16(DMA2_1_Y_MODIFY, val)

#define bfin_write_DMA2_2_CONFIG ( val   )     bfin_write16(DMA2_2_CONFIG, val)

#define bfin_write_DMA2_2_CURR_ADDR ( val   )     bfin_writePTR(DMA2_2_CURR_ADDR, val)

#define bfin_write_DMA2_2_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)

#define bfin_write_DMA2_2_CURR_X_COUNT ( val   )     bfin_write16(DMA2_2_CURR_X_COUNT, val)

#define bfin_write_DMA2_2_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_2_CURR_Y_COUNT, val)

#define bfin_write_DMA2_2_IRQ_STATUS ( val   )     bfin_write16(DMA2_2_IRQ_STATUS, val)

#define bfin_write_DMA2_2_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_2_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_2_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_2_START_ADDR ( val   )     bfin_writePTR(DMA2_2_START_ADDR, val)

#define bfin_write_DMA2_2_X_COUNT ( val   )     bfin_write16(DMA2_2_X_COUNT, val)

#define bfin_write_DMA2_2_X_MODIFY ( val   )     bfin_write16(DMA2_2_X_MODIFY, val)

#define bfin_write_DMA2_2_Y_COUNT ( val   )     bfin_write16(DMA2_2_Y_COUNT, val)

#define bfin_write_DMA2_2_Y_MODIFY ( val   )     bfin_write16(DMA2_2_Y_MODIFY, val)

#define bfin_write_DMA2_3_CONFIG ( val   )     bfin_write16(DMA2_3_CONFIG, val)

#define bfin_write_DMA2_3_CURR_ADDR ( val   )     bfin_writePTR(DMA2_3_CURR_ADDR, val)

#define bfin_write_DMA2_3_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)

#define bfin_write_DMA2_3_CURR_X_COUNT ( val   )     bfin_write16(DMA2_3_CURR_X_COUNT, val)

#define bfin_write_DMA2_3_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_3_CURR_Y_COUNT, val)

#define bfin_write_DMA2_3_IRQ_STATUS ( val   )     bfin_write16(DMA2_3_IRQ_STATUS, val)

#define bfin_write_DMA2_3_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_3_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_3_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_3_START_ADDR ( val   )     bfin_writePTR(DMA2_3_START_ADDR, val)

#define bfin_write_DMA2_3_X_COUNT ( val   )     bfin_write16(DMA2_3_X_COUNT, val)

#define bfin_write_DMA2_3_X_MODIFY ( val   )     bfin_write16(DMA2_3_X_MODIFY, val)

#define bfin_write_DMA2_3_Y_COUNT ( val   )     bfin_write16(DMA2_3_Y_COUNT, val)

#define bfin_write_DMA2_3_Y_MODIFY ( val   )     bfin_write16(DMA2_3_Y_MODIFY, val)

#define bfin_write_DMA2_4_CONFIG ( val   )     bfin_write16(DMA2_4_CONFIG, val)

#define bfin_write_DMA2_4_CURR_ADDR ( val   )     bfin_writePTR(DMA2_4_CURR_ADDR, val)

#define bfin_write_DMA2_4_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)

#define bfin_write_DMA2_4_CURR_X_COUNT ( val   )     bfin_write16(DMA2_4_CURR_X_COUNT, val)

#define bfin_write_DMA2_4_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_4_CURR_Y_COUNT, val)

#define bfin_write_DMA2_4_IRQ_STATUS ( val   )     bfin_write16(DMA2_4_IRQ_STATUS, val)

#define bfin_write_DMA2_4_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_4_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_4_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_4_START_ADDR ( val   )     bfin_writePTR(DMA2_4_START_ADDR, val)

#define bfin_write_DMA2_4_X_COUNT ( val   )     bfin_write16(DMA2_4_X_COUNT, val)

#define bfin_write_DMA2_4_X_MODIFY ( val   )     bfin_write16(DMA2_4_X_MODIFY, val)

#define bfin_write_DMA2_4_Y_COUNT ( val   )     bfin_write16(DMA2_4_Y_COUNT, val)

#define bfin_write_DMA2_4_Y_MODIFY ( val   )     bfin_write16(DMA2_4_Y_MODIFY, val)

#define bfin_write_DMA2_5_CONFIG ( val   )     bfin_write16(DMA2_5_CONFIG, val)

#define bfin_write_DMA2_5_CURR_ADDR ( val   )     bfin_writePTR(DMA2_5_CURR_ADDR, val)

#define bfin_write_DMA2_5_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)

#define bfin_write_DMA2_5_CURR_X_COUNT ( val   )     bfin_write16(DMA2_5_CURR_X_COUNT, val)

#define bfin_write_DMA2_5_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_5_CURR_Y_COUNT, val)

#define bfin_write_DMA2_5_IRQ_STATUS ( val   )     bfin_write16(DMA2_5_IRQ_STATUS, val)

#define bfin_write_DMA2_5_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_5_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_5_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_5_START_ADDR ( val   )     bfin_writePTR(DMA2_5_START_ADDR, val)

#define bfin_write_DMA2_5_X_COUNT ( val   )     bfin_write16(DMA2_5_X_COUNT, val)

#define bfin_write_DMA2_5_X_MODIFY ( val   )     bfin_write16(DMA2_5_X_MODIFY, val)

#define bfin_write_DMA2_5_Y_COUNT ( val   )     bfin_write16(DMA2_5_Y_COUNT, val)

#define bfin_write_DMA2_5_Y_MODIFY ( val   )     bfin_write16(DMA2_5_Y_MODIFY, val)

#define bfin_write_DMA2_6_CONFIG ( val   )     bfin_write16(DMA2_6_CONFIG, val)

#define bfin_write_DMA2_6_CURR_ADDR ( val   )     bfin_writePTR(DMA2_6_CURR_ADDR, val)

#define bfin_write_DMA2_6_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)

#define bfin_write_DMA2_6_CURR_X_COUNT ( val   )     bfin_write16(DMA2_6_CURR_X_COUNT, val)

#define bfin_write_DMA2_6_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_6_CURR_Y_COUNT, val)

#define bfin_write_DMA2_6_IRQ_STATUS ( val   )     bfin_write16(DMA2_6_IRQ_STATUS, val)

#define bfin_write_DMA2_6_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_6_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_6_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_6_START_ADDR ( val   )     bfin_writePTR(DMA2_6_START_ADDR, val)

#define bfin_write_DMA2_6_X_COUNT ( val   )     bfin_write16(DMA2_6_X_COUNT, val)

#define bfin_write_DMA2_6_X_MODIFY ( val   )     bfin_write16(DMA2_6_X_MODIFY, val)

#define bfin_write_DMA2_6_Y_COUNT ( val   )     bfin_write16(DMA2_6_Y_COUNT, val)

#define bfin_write_DMA2_6_Y_MODIFY ( val   )     bfin_write16(DMA2_6_Y_MODIFY, val)

#define bfin_write_DMA2_7_CONFIG ( val   )     bfin_write16(DMA2_7_CONFIG, val)

#define bfin_write_DMA2_7_CURR_ADDR ( val   )     bfin_writePTR(DMA2_7_CURR_ADDR, val)

#define bfin_write_DMA2_7_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)

#define bfin_write_DMA2_7_CURR_X_COUNT ( val   )     bfin_write16(DMA2_7_CURR_X_COUNT, val)

#define bfin_write_DMA2_7_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_7_CURR_Y_COUNT, val)

#define bfin_write_DMA2_7_IRQ_STATUS ( val   )     bfin_write16(DMA2_7_IRQ_STATUS, val)

#define bfin_write_DMA2_7_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_7_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_7_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_7_START_ADDR ( val   )     bfin_writePTR(DMA2_7_START_ADDR, val)

#define bfin_write_DMA2_7_X_COUNT ( val   )     bfin_write16(DMA2_7_X_COUNT, val)

#define bfin_write_DMA2_7_X_MODIFY ( val   )     bfin_write16(DMA2_7_X_MODIFY, val)

#define bfin_write_DMA2_7_Y_COUNT ( val   )     bfin_write16(DMA2_7_Y_COUNT, val)

#define bfin_write_DMA2_7_Y_MODIFY ( val   )     bfin_write16(DMA2_7_Y_MODIFY, val)

#define bfin_write_DMA2_8_CONFIG ( val   )     bfin_write16(DMA2_8_CONFIG, val)

#define bfin_write_DMA2_8_CURR_ADDR ( val   )     bfin_writePTR(DMA2_8_CURR_ADDR, val)

#define bfin_write_DMA2_8_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)

#define bfin_write_DMA2_8_CURR_X_COUNT ( val   )     bfin_write16(DMA2_8_CURR_X_COUNT, val)

#define bfin_write_DMA2_8_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_8_CURR_Y_COUNT, val)

#define bfin_write_DMA2_8_IRQ_STATUS ( val   )     bfin_write16(DMA2_8_IRQ_STATUS, val)

#define bfin_write_DMA2_8_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_8_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_8_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_8_START_ADDR ( val   )     bfin_writePTR(DMA2_8_START_ADDR, val)

#define bfin_write_DMA2_8_X_COUNT ( val   )     bfin_write16(DMA2_8_X_COUNT, val)

#define bfin_write_DMA2_8_X_MODIFY ( val   )     bfin_write16(DMA2_8_X_MODIFY, val)

#define bfin_write_DMA2_8_Y_COUNT ( val   )     bfin_write16(DMA2_8_Y_COUNT, val)

#define bfin_write_DMA2_8_Y_MODIFY ( val   )     bfin_write16(DMA2_8_Y_MODIFY, val)

#define bfin_write_DMA2_9_CONFIG ( val   )     bfin_write16(DMA2_9_CONFIG, val)

#define bfin_write_DMA2_9_CURR_ADDR ( val   )     bfin_writePTR(DMA2_9_CURR_ADDR, val)

#define bfin_write_DMA2_9_CURR_DESC_PTR ( val   )     bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)

#define bfin_write_DMA2_9_CURR_X_COUNT ( val   )     bfin_write16(DMA2_9_CURR_X_COUNT, val)

#define bfin_write_DMA2_9_CURR_Y_COUNT ( val   )     bfin_write16(DMA2_9_CURR_Y_COUNT, val)

#define bfin_write_DMA2_9_IRQ_STATUS ( val   )     bfin_write16(DMA2_9_IRQ_STATUS, val)

#define bfin_write_DMA2_9_NEXT_DESC_PTR ( val   )     bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)

#define bfin_write_DMA2_9_PERIPHERAL_MAP ( val   )     bfin_write16(DMA2_9_PERIPHERAL_MAP, val)

#define bfin_write_DMA2_9_START_ADDR ( val   )     bfin_writePTR(DMA2_9_START_ADDR, val)

#define bfin_write_DMA2_9_X_COUNT ( val   )     bfin_write16(DMA2_9_X_COUNT, val)

#define bfin_write_DMA2_9_X_MODIFY ( val   )     bfin_write16(DMA2_9_X_MODIFY, val)

#define bfin_write_DMA2_9_Y_COUNT ( val   )     bfin_write16(DMA2_9_Y_COUNT, val)

#define bfin_write_DMA2_9_Y_MODIFY ( val   )     bfin_write16(DMA2_9_Y_MODIFY, val)

#define bfin_write_DMA2_TC_CNT ( val   )     bfin_write16(DMA2_TC_CNT, val)

#define bfin_write_DMA2_TC_PER ( val   )     bfin_write16(DMA2_TC_PER, val)

#define bfin_write_EVT0 ( val   )     bfin_writePTR(EVT0, val)

#define bfin_write_EVT1 ( val   )     bfin_writePTR(EVT1, val)

#define bfin_write_EVT10 ( val   )     bfin_writePTR(EVT10, val)

#define bfin_write_EVT11 ( val   )     bfin_writePTR(EVT11, val)

#define bfin_write_EVT12 ( val   )     bfin_writePTR(EVT12, val)

#define bfin_write_EVT13 ( val   )     bfin_writePTR(EVT13, val)

#define bfin_write_EVT14 ( val   )     bfin_writePTR(EVT14, val)

#define bfin_write_EVT15 ( val   )     bfin_writePTR(EVT15, val)

#define bfin_write_EVT2 ( val   )     bfin_writePTR(EVT2, val)

#define bfin_write_EVT3 ( val   )     bfin_writePTR(EVT3, val)

#define bfin_write_EVT4 ( val   )     bfin_writePTR(EVT4, val)

#define bfin_write_EVT5 ( val   )     bfin_writePTR(EVT5, val)

#define bfin_write_EVT6 ( val   )     bfin_writePTR(EVT6, val)

#define bfin_write_EVT7 ( val   )     bfin_writePTR(EVT7, val)

#define bfin_write_EVT8 ( val   )     bfin_writePTR(EVT8, val)

#define bfin_write_EVT9 ( val   )     bfin_writePTR(EVT9, val)

#define bfin_write_FIO0_BOTH ( val   )     bfin_write16(FIO0_BOTH, val)

#define bfin_write_FIO0_DIR ( val   )     bfin_write16(FIO0_DIR, val)

#define bfin_write_FIO0_EDGE ( val   )     bfin_write16(FIO0_EDGE, val)

#define bfin_write_FIO0_FLAG_C ( val   )     bfin_write16(FIO0_FLAG_C, val)

#define bfin_write_FIO0_FLAG_D ( val   )     bfin_write16(FIO0_FLAG_D, val)

#define bfin_write_FIO0_FLAG_S ( val   )     bfin_write16(FIO0_FLAG_S, val)

#define bfin_write_FIO0_FLAG_T ( val   )     bfin_write16(FIO0_FLAG_T, val)

#define bfin_write_FIO0_INEN ( val   )     bfin_write16(FIO0_INEN, val)

#define bfin_write_FIO0_MASKA_C ( val   )     bfin_write16(FIO0_MASKA_C, val)

#define bfin_write_FIO0_MASKA_D ( val   )     bfin_write16(FIO0_MASKA_D, val)

#define bfin_write_FIO0_MASKA_S ( val   )     bfin_write16(FIO0_MASKA_S, val)

#define bfin_write_FIO0_MASKA_T ( val   )     bfin_write16(FIO0_MASKA_T, val)

#define bfin_write_FIO0_MASKB_C ( val   )     bfin_write16(FIO0_MASKB_C, val)

#define bfin_write_FIO0_MASKB_D ( val   )     bfin_write16(FIO0_MASKB_D, val)

#define bfin_write_FIO0_MASKB_S ( val   )     bfin_write16(FIO0_MASKB_S, val)

#define bfin_write_FIO0_MASKB_T ( val   )     bfin_write16(FIO0_MASKB_T, val)

#define bfin_write_FIO0_POLAR ( val   )     bfin_write16(FIO0_POLAR, val)

#define bfin_write_FIO1_BOTH ( val   )     bfin_write16(FIO1_BOTH, val)

#define bfin_write_FIO1_DIR ( val   )     bfin_write16(FIO1_DIR, val)

#define bfin_write_FIO1_EDGE ( val   )     bfin_write16(FIO1_EDGE, val)

#define bfin_write_FIO1_FLAG_C ( val   )     bfin_write16(FIO1_FLAG_C, val)

#define bfin_write_FIO1_FLAG_D ( val   )     bfin_write16(FIO1_FLAG_D, val)

#define bfin_write_FIO1_FLAG_S ( val   )     bfin_write16(FIO1_FLAG_S, val)

#define bfin_write_FIO1_FLAG_T ( val   )     bfin_write16(FIO1_FLAG_T, val)

#define bfin_write_FIO1_INEN ( val   )     bfin_write16(FIO1_INEN, val)

#define bfin_write_FIO1_MASKA_C ( val   )     bfin_write16(FIO1_MASKA_C, val)

#define bfin_write_FIO1_MASKA_D ( val   )     bfin_write16(FIO1_MASKA_D, val)

#define bfin_write_FIO1_MASKA_S ( val   )     bfin_write16(FIO1_MASKA_S, val)

#define bfin_write_FIO1_MASKA_T ( val   )     bfin_write16(FIO1_MASKA_T, val)

#define bfin_write_FIO1_MASKB_C ( val   )     bfin_write16(FIO1_MASKB_C, val)

#define bfin_write_FIO1_MASKB_D ( val   )     bfin_write16(FIO1_MASKB_D, val)

#define bfin_write_FIO1_MASKB_S ( val   )     bfin_write16(FIO1_MASKB_S, val)

#define bfin_write_FIO1_MASKB_T ( val   )     bfin_write16(FIO1_MASKB_T, val)

#define bfin_write_FIO1_POLAR ( val   )     bfin_write16(FIO1_POLAR, val)

#define bfin_write_FIO2_BOTH ( val   )     bfin_write16(FIO2_BOTH, val)

#define bfin_write_FIO2_DIR ( val   )     bfin_write16(FIO2_DIR, val)

#define bfin_write_FIO2_EDGE ( val   )     bfin_write16(FIO2_EDGE, val)

#define bfin_write_FIO2_FLAG_C ( val   )     bfin_write16(FIO2_FLAG_C, val)

#define bfin_write_FIO2_FLAG_D ( val   )     bfin_write16(FIO2_FLAG_D, val)

#define bfin_write_FIO2_FLAG_S ( val   )     bfin_write16(FIO2_FLAG_S, val)

#define bfin_write_FIO2_FLAG_T ( val   )     bfin_write16(FIO2_FLAG_T, val)

#define bfin_write_FIO2_INEN ( val   )     bfin_write16(FIO2_INEN, val)

#define bfin_write_FIO2_MASKA_C ( val   )     bfin_write16(FIO2_MASKA_C, val)

#define bfin_write_FIO2_MASKA_D ( val   )     bfin_write16(FIO2_MASKA_D, val)

#define bfin_write_FIO2_MASKA_S ( val   )     bfin_write16(FIO2_MASKA_S, val)

#define bfin_write_FIO2_MASKA_T ( val   )     bfin_write16(FIO2_MASKA_T, val)

#define bfin_write_FIO2_MASKB_C ( val   )     bfin_write16(FIO2_MASKB_C, val)

#define bfin_write_FIO2_MASKB_D ( val   )     bfin_write16(FIO2_MASKB_D, val)

#define bfin_write_FIO2_MASKB_S ( val   )     bfin_write16(FIO2_MASKB_S, val)

#define bfin_write_FIO2_MASKB_T ( val   )     bfin_write16(FIO2_MASKB_T, val)

#define bfin_write_FIO2_POLAR ( val   )     bfin_write16(FIO2_POLAR, val)

#define bfin_write_ILAT ( val   )     bfin_write32(ILAT, val)

#define bfin_write_IMASK ( val   )     bfin_write32(IMASK, val)

#define bfin_write_IMDMA_D0_CONFIG ( val   )     bfin_write16(IMDMA_D0_CONFIG, val)

#define bfin_write_IMDMA_D0_CURR_ADDR ( val   )     bfin_writePTR(IMDMA_D0_CURR_ADDR, val)

#define bfin_write_IMDMA_D0_CURR_DESC_PTR ( val   )     bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)

#define bfin_write_IMDMA_D0_CURR_X_COUNT ( val   )     bfin_write16(IMDMA_D0_CURR_X_COUNT, val)

#define bfin_write_IMDMA_D0_CURR_Y_COUNT ( val   )     bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)

#define bfin_write_IMDMA_D0_IRQ_STATUS ( val   )     bfin_write16(IMDMA_D0_IRQ_STATUS, val)

#define bfin_write_IMDMA_D0_NEXT_DESC_PTR ( val   )     bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)

#define bfin_write_IMDMA_D0_START_ADDR ( val   )     bfin_writePTR(IMDMA_D0_START_ADDR, val)

#define bfin_write_IMDMA_D0_X_COUNT ( val   )     bfin_write16(IMDMA_D0_X_COUNT, val)

#define bfin_write_IMDMA_D0_X_MODIFY ( val   )     bfin_write16(IMDMA_D0_X_MODIFY, val)

#define bfin_write_IMDMA_D0_Y_COUNT ( val   )     bfin_write16(IMDMA_D0_Y_COUNT, val)

#define bfin_write_IMDMA_D0_Y_MODIFY ( val   )     bfin_write16(IMDMA_D0_Y_MODIFY, val)

#define bfin_write_IMDMA_D1_CONFIG ( val   )     bfin_write16(IMDMA_D1_CONFIG, val)

#define bfin_write_IMDMA_D1_CURR_ADDR ( val   )     bfin_writePTR(IMDMA_D1_CURR_ADDR, val)

#define bfin_write_IMDMA_D1_CURR_DESC_PTR ( val   )     bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)

#define bfin_write_IMDMA_D1_CURR_X_COUNT ( val   )     bfin_write16(IMDMA_D1_CURR_X_COUNT, val)

#define bfin_write_IMDMA_D1_CURR_Y_COUNT ( val   )     bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)

#define bfin_write_IMDMA_D1_IRQ_STATUS ( val   )     bfin_write16(IMDMA_D1_IRQ_STATUS, val)

#define bfin_write_IMDMA_D1_NEXT_DESC_PTR ( val   )     bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)

#define bfin_write_IMDMA_D1_START_ADDR ( val   )     bfin_writePTR(IMDMA_D1_START_ADDR, val)

#define bfin_write_IMDMA_D1_X_COUNT ( val   )     bfin_write16(IMDMA_D1_X_COUNT, val)

#define bfin_write_IMDMA_D1_X_MODIFY ( val   )     bfin_write16(IMDMA_D1_X_MODIFY, val)

#define bfin_write_IMDMA_D1_Y_COUNT ( val   )     bfin_write16(IMDMA_D1_Y_COUNT, val)

#define bfin_write_IMDMA_D1_Y_MODIFY ( val   )     bfin_write16(IMDMA_D1_Y_MODIFY, val)

#define bfin_write_IMDMA_S0_CONFIG ( val   )     bfin_write16(IMDMA_S0_CONFIG, val)

#define bfin_write_IMDMA_S0_CURR_ADDR ( val   )     bfin_writePTR(IMDMA_S0_CURR_ADDR, val)

#define bfin_write_IMDMA_S0_CURR_DESC_PTR ( val   )     bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)

#define bfin_write_IMDMA_S0_CURR_X_COUNT ( val   )     bfin_write16(IMDMA_S0_CURR_X_COUNT, val)

#define bfin_write_IMDMA_S0_CURR_Y_COUNT ( val   )     bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)

#define bfin_write_IMDMA_S0_IRQ_STATUS ( val   )     bfin_write16(IMDMA_S0_IRQ_STATUS, val)

#define bfin_write_IMDMA_S0_NEXT_DESC_PTR ( val   )     bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)

#define bfin_write_IMDMA_S0_START_ADDR ( val   )     bfin_writePTR(IMDMA_S0_START_ADDR, val)

#define bfin_write_IMDMA_S0_X_COUNT ( val   )     bfin_write16(IMDMA_S0_X_COUNT, val)

#define bfin_write_IMDMA_S0_X_MODIFY ( val   )     bfin_write16(IMDMA_S0_X_MODIFY, val)

#define bfin_write_IMDMA_S0_Y_COUNT ( val   )     bfin_write16(IMDMA_S0_Y_COUNT, val)

#define bfin_write_IMDMA_S0_Y_MODIFY ( val   )     bfin_write16(IMDMA_S0_Y_MODIFY, val)

#define bfin_write_IMDMA_S1_CONFIG ( val   )     bfin_write16(IMDMA_S1_CONFIG, val)

#define bfin_write_IMDMA_S1_CURR_ADDR ( val   )     bfin_writePTR(IMDMA_S1_CURR_ADDR, val)

#define bfin_write_IMDMA_S1_CURR_DESC_PTR ( val   )     bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)

#define bfin_write_IMDMA_S1_CURR_X_COUNT ( val   )     bfin_write16(IMDMA_S1_CURR_X_COUNT, val)

#define bfin_write_IMDMA_S1_CURR_Y_COUNT ( val   )     bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)

#define bfin_write_IMDMA_S1_IRQ_STATUS ( val   )     bfin_write16(IMDMA_S1_IRQ_STATUS, val)

#define bfin_write_IMDMA_S1_NEXT_DESC_PTR ( val   )     bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)

#define bfin_write_IMDMA_S1_START_ADDR ( val   )     bfin_writePTR(IMDMA_S1_START_ADDR, val)

#define bfin_write_IMDMA_S1_X_COUNT ( val   )     bfin_write16(IMDMA_S1_X_COUNT, val)

#define bfin_write_IMDMA_S1_X_MODIFY ( val   )     bfin_write16(IMDMA_S1_X_MODIFY, val)

#define bfin_write_IMDMA_S1_Y_COUNT ( val   )     bfin_write16(IMDMA_S1_Y_COUNT, val)

#define bfin_write_IMDMA_S1_Y_MODIFY ( val   )     bfin_write16(IMDMA_S1_Y_MODIFY, val)

#define bfin_write_IPEND ( val   )     bfin_write32(IPEND, val)

#define bfin_write_IPRIO ( val   )     bfin_write32(IPRIO, val)

#define bfin_write_MDMA1_D0_CONFIG ( val   )     bfin_write16(MDMA1_D0_CONFIG, val)

#define bfin_write_MDMA1_D0_CURR_ADDR ( val   )     bfin_writePTR(MDMA1_D0_CURR_ADDR, val)

#define bfin_write_MDMA1_D0_CURR_DESC_PTR ( val   )     bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)

#define bfin_write_MDMA1_D0_CURR_X_COUNT ( val   )     bfin_write16(MDMA1_D0_CURR_X_COUNT, val)

#define bfin_write_MDMA1_D0_CURR_Y_COUNT ( val   )     bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)

#define bfin_write_MDMA1_D0_IRQ_STATUS ( val   )     bfin_write16(MDMA1_D0_IRQ_STATUS, val)

#define bfin_write_MDMA1_D0_NEXT_DESC_PTR ( val   )     bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)

#define bfin_write_MDMA1_D0_PERIPHERAL_MAP ( val   )     bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)

#define bfin_write_MDMA1_D0_START_ADDR ( val   )     bfin_writePTR(MDMA1_D0_START_ADDR, val)

#define bfin_write_MDMA1_D0_X_COUNT ( val   )     bfin_write16(MDMA1_D0_X_COUNT, val)

#define bfin_write_MDMA1_D0_X_MODIFY ( val   )     bfin_write16(MDMA1_D0_X_MODIFY, val)

#define bfin_write_MDMA1_D0_Y_COUNT ( val   )     bfin_write16(MDMA1_D0_Y_COUNT, val)

#define bfin_write_MDMA1_D0_Y_MODIFY ( val   )     bfin_write16(MDMA1_D0_Y_MODIFY, val)

#define bfin_write_MDMA1_D1_CONFIG ( val   )     bfin_write16(MDMA1_D1_CONFIG, val)

#define bfin_write_MDMA1_D1_CURR_ADDR ( val   )     bfin_writePTR(MDMA1_D1_CURR_ADDR, val)

#define bfin_write_MDMA1_D1_CURR_DESC_PTR ( val   )     bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)

#define bfin_write_MDMA1_D1_CURR_X_COUNT ( val   )     bfin_write16(MDMA1_D1_CURR_X_COUNT, val)

#define bfin_write_MDMA1_D1_CURR_Y_COUNT ( val   )     bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)

#define bfin_write_MDMA1_D1_IRQ_STATUS ( val   )     bfin_write16(MDMA1_D1_IRQ_STATUS, val)

#define bfin_write_MDMA1_D1_NEXT_DESC_PTR ( val   )     bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)

#define bfin_write_MDMA1_D1_PERIPHERAL_MAP ( val   )     bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)

#define bfin_write_MDMA1_D1_START_ADDR ( val   )     bfin_writePTR(MDMA1_D1_START_ADDR, val)

#define bfin_write_MDMA1_D1_X_COUNT ( val   )     bfin_write16(MDMA1_D1_X_COUNT, val)

#define bfin_write_MDMA1_D1_X_MODIFY ( val   )     bfin_write16(MDMA1_D1_X_MODIFY, val)

#define bfin_write_MDMA1_D1_Y_COUNT ( val   )     bfin_write16(MDMA1_D1_Y_COUNT, val)

#define bfin_write_MDMA1_D1_Y_MODIFY ( val   )     bfin_write16(MDMA1_D1_Y_MODIFY, val)

#define bfin_write_MDMA1_S0_CONFIG ( val   )     bfin_write16(MDMA1_S0_CONFIG, val)

#define bfin_write_MDMA1_S0_CURR_ADDR ( val   )     bfin_writePTR(MDMA1_S0_CURR_ADDR, val)

#define bfin_write_MDMA1_S0_CURR_DESC_PTR ( val   )     bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)

#define bfin_write_MDMA1_S0_CURR_X_COUNT ( val   )     bfin_write16(MDMA1_S0_CURR_X_COUNT, val)

#define bfin_write_MDMA1_S0_CURR_Y_COUNT ( val   )     bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)

#define bfin_write_MDMA1_S0_IRQ_STATUS ( val   )     bfin_write16(MDMA1_S0_IRQ_STATUS, val)

#define bfin_write_MDMA1_S0_NEXT_DESC_PTR ( val   )     bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)

#define bfin_write_MDMA1_S0_PERIPHERAL_MAP ( val   )     bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)

#define bfin_write_MDMA1_S0_START_ADDR ( val   )     bfin_writePTR(MDMA1_S0_START_ADDR, val)

#define bfin_write_MDMA1_S0_X_COUNT ( val   )     bfin_write16(MDMA1_S0_X_COUNT, val)

#define bfin_write_MDMA1_S0_X_MODIFY ( val   )     bfin_write16(MDMA1_S0_X_MODIFY, val)

#define bfin_write_MDMA1_S0_Y_COUNT ( val   )     bfin_write16(MDMA1_S0_Y_COUNT, val)

#define bfin_write_MDMA1_S0_Y_MODIFY ( val   )     bfin_write16(MDMA1_S0_Y_MODIFY, val)

#define bfin_write_MDMA1_S1_CONFIG ( val   )     bfin_write16(MDMA1_S1_CONFIG, val)

#define bfin_write_MDMA1_S1_CURR_ADDR ( val   )     bfin_writePTR(MDMA1_S1_CURR_ADDR, val)

#define bfin_write_MDMA1_S1_CURR_DESC_PTR ( val   )     bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)

#define bfin_write_MDMA1_S1_CURR_X_COUNT ( val   )     bfin_write16(MDMA1_S1_CURR_X_COUNT, val)

#define bfin_write_MDMA1_S1_CURR_Y_COUNT ( val   )     bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)

#define bfin_write_MDMA1_S1_IRQ_STATUS ( val   )     bfin_write16(MDMA1_S1_IRQ_STATUS, val)

#define bfin_write_MDMA1_S1_NEXT_DESC_PTR ( val   )     bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)

#define bfin_write_MDMA1_S1_PERIPHERAL_MAP ( val   )     bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)

#define bfin_write_MDMA1_S1_START_ADDR ( val   )     bfin_writePTR(MDMA1_S1_START_ADDR, val)

#define bfin_write_MDMA1_S1_X_COUNT ( val   )     bfin_write16(MDMA1_S1_X_COUNT, val)

#define bfin_write_MDMA1_S1_X_MODIFY ( val   )     bfin_write16(MDMA1_S1_X_MODIFY, val)

#define bfin_write_MDMA1_S1_Y_COUNT ( val   )     bfin_write16(MDMA1_S1_Y_COUNT, val)

#define bfin_write_MDMA1_S1_Y_MODIFY ( val   )     bfin_write16(MDMA1_S1_Y_MODIFY, val)

#define bfin_write_MDMA2_D0_CONFIG ( val   )     bfin_write16(MDMA2_D0_CONFIG, val)

#define bfin_write_MDMA2_D0_CURR_ADDR ( val   )     bfin_writePTR(MDMA2_D0_CURR_ADDR, val)

#define bfin_write_MDMA2_D0_CURR_DESC_PTR ( val   )     bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)

#define bfin_write_MDMA2_D0_CURR_X_COUNT ( val   )     bfin_write16(MDMA2_D0_CURR_X_COUNT, val)

#define bfin_write_MDMA2_D0_CURR_Y_COUNT ( val   )     bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)

#define bfin_write_MDMA2_D0_IRQ_STATUS ( val   )     bfin_write16(MDMA2_D0_IRQ_STATUS, val)

#define bfin_write_MDMA2_D0_NEXT_DESC_PTR ( val   )     bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)

#define bfin_write_MDMA2_D0_PERIPHERAL_MAP ( val   )     bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)

#define bfin_write_MDMA2_D0_START_ADDR ( val   )     bfin_writePTR(MDMA2_D0_START_ADDR, val)

#define bfin_write_MDMA2_D0_X_COUNT ( val   )     bfin_write16(MDMA2_D0_X_COUNT, val)

#define bfin_write_MDMA2_D0_X_MODIFY ( val   )     bfin_write16(MDMA2_D0_X_MODIFY, val)

#define bfin_write_MDMA2_D0_Y_COUNT ( val   )     bfin_write16(MDMA2_D0_Y_COUNT, val)

#define bfin_write_MDMA2_D0_Y_MODIFY ( val   )     bfin_write16(MDMA2_D0_Y_MODIFY, val)

#define bfin_write_MDMA2_D1_CONFIG ( val   )     bfin_write16(MDMA2_D1_CONFIG, val)

#define bfin_write_MDMA2_D1_CURR_ADDR ( val   )     bfin_writePTR(MDMA2_D1_CURR_ADDR, val)

#define bfin_write_MDMA2_D1_CURR_DESC_PTR ( val   )     bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)

#define bfin_write_MDMA2_D1_CURR_X_COUNT ( val   )     bfin_write16(MDMA2_D1_CURR_X_COUNT, val)

#define bfin_write_MDMA2_D1_CURR_Y_COUNT ( val   )     bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)

#define bfin_write_MDMA2_D1_IRQ_STATUS ( val   )     bfin_write16(MDMA2_D1_IRQ_STATUS, val)

#define bfin_write_MDMA2_D1_NEXT_DESC_PTR ( val   )     bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)

#define bfin_write_MDMA2_D1_PERIPHERAL_MAP ( val   )     bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)

#define bfin_write_MDMA2_D1_START_ADDR ( val   )     bfin_writePTR(MDMA2_D1_START_ADDR, val)

#define bfin_write_MDMA2_D1_X_COUNT ( val   )     bfin_write16(MDMA2_D1_X_COUNT, val)

#define bfin_write_MDMA2_D1_X_MODIFY ( val   )     bfin_write16(MDMA2_D1_X_MODIFY, val)

#define bfin_write_MDMA2_D1_Y_COUNT ( val   )     bfin_write16(MDMA2_D1_Y_COUNT, val)

#define bfin_write_MDMA2_D1_Y_MODIFY ( val   )     bfin_write16(MDMA2_D1_Y_MODIFY, val)

#define bfin_write_MDMA2_S0_CONFIG ( val   )     bfin_write16(MDMA2_S0_CONFIG, val)

#define bfin_write_MDMA2_S0_CURR_ADDR ( val   )     bfin_writePTR(MDMA2_S0_CURR_ADDR, val)

#define bfin_write_MDMA2_S0_CURR_DESC_PTR ( val   )     bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)

#define bfin_write_MDMA2_S0_CURR_X_COUNT ( val   )     bfin_write16(MDMA2_S0_CURR_X_COUNT, val)

#define bfin_write_MDMA2_S0_CURR_Y_COUNT ( val   )     bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)

#define bfin_write_MDMA2_S0_IRQ_STATUS ( val   )     bfin_write16(MDMA2_S0_IRQ_STATUS, val)

#define bfin_write_MDMA2_S0_NEXT_DESC_PTR ( val   )     bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)

#define bfin_write_MDMA2_S0_PERIPHERAL_MAP ( val   )     bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)

#define bfin_write_MDMA2_S0_START_ADDR ( val   )     bfin_writePTR(MDMA2_S0_START_ADDR, val)

#define bfin_write_MDMA2_S0_X_COUNT ( val   )     bfin_write16(MDMA2_S0_X_COUNT, val)

#define bfin_write_MDMA2_S0_X_MODIFY ( val   )     bfin_write16(MDMA2_S0_X_MODIFY, val)

#define bfin_write_MDMA2_S0_Y_COUNT ( val   )     bfin_write16(MDMA2_S0_Y_COUNT, val)

#define bfin_write_MDMA2_S0_Y_MODIFY ( val   )     bfin_write16(MDMA2_S0_Y_MODIFY, val)

#define bfin_write_MDMA2_S1_CONFIG ( val   )     bfin_write16(MDMA2_S1_CONFIG, val)

#define bfin_write_MDMA2_S1_CURR_ADDR ( val   )     bfin_writePTR(MDMA2_S1_CURR_ADDR, val)

#define bfin_write_MDMA2_S1_CURR_DESC_PTR ( val   )     bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)

#define bfin_write_MDMA2_S1_CURR_X_COUNT ( val   )     bfin_write16(MDMA2_S1_CURR_X_COUNT, val)

#define bfin_write_MDMA2_S1_CURR_Y_COUNT ( val   )     bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)

#define bfin_write_MDMA2_S1_IRQ_STATUS ( val   )     bfin_write16(MDMA2_S1_IRQ_STATUS, val)

#define bfin_write_MDMA2_S1_NEXT_DESC_PTR ( val   )     bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)

#define bfin_write_MDMA2_S1_PERIPHERAL_MAP ( val   )     bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)

#define bfin_write_MDMA2_S1_START_ADDR ( val   )     bfin_writePTR(MDMA2_S1_START_ADDR, val)

#define bfin_write_MDMA2_S1_X_COUNT ( val   )     bfin_write16(MDMA2_S1_X_COUNT, val)

#define bfin_write_MDMA2_S1_X_MODIFY ( val   )     bfin_write16(MDMA2_S1_X_MODIFY, val)

#define bfin_write_MDMA2_S1_Y_COUNT ( val   )     bfin_write16(MDMA2_S1_Y_COUNT, val)

#define bfin_write_MDMA2_S1_Y_MODIFY ( val   )     bfin_write16(MDMA2_S1_Y_MODIFY, val)

#define bfin_write_PLL_CTL ( val   )     bfin_write16(PLL_CTL, val)

#define bfin_write_PLL_DIV ( val   )     bfin_write16(PLL_DIV, val)

#define bfin_write_PLL_LOCKCNT ( val   )     bfin_write16(PLL_LOCKCNT, val)

#define bfin_write_PLL_STAT ( val   )     bfin_write16(PLL_STAT, val)

#define bfin_write_SPI_BAUD ( val   )     bfin_write16(SPI_BAUD, val)

#define bfin_write_SPI_CTL ( val   )     bfin_write16(SPI_CTL, val)

#define bfin_write_SPI_FLG ( val   )     bfin_write16(SPI_FLG, val)

#define bfin_write_SPI_RDBR ( val   )     bfin_write16(SPI_RDBR, val)

#define bfin_write_SPI_SHADOW ( val   )     bfin_write16(SPI_SHADOW, val)

#define bfin_write_SPI_STAT ( val   )     bfin_write16(SPI_STAT, val)

#define bfin_write_SPI_TDBR ( val   )     bfin_write16(SPI_TDBR, val)

#define bfin_write_SPORT0_CHNL ( val   )     bfin_write16(SPORT0_CHNL, val)

#define bfin_write_SPORT0_MCMC1 ( val   )     bfin_write16(SPORT0_MCMC1, val)

#define bfin_write_SPORT0_MCMC2 ( val   )     bfin_write16(SPORT0_MCMC2, val)

#define bfin_write_SPORT0_MRCS0 ( val   )     bfin_write32(SPORT0_MRCS0, val)

#define bfin_write_SPORT0_MRCS1 ( val   )     bfin_write32(SPORT0_MRCS1, val)

#define bfin_write_SPORT0_MRCS2 ( val   )     bfin_write32(SPORT0_MRCS2, val)

#define bfin_write_SPORT0_MRCS3 ( val   )     bfin_write32(SPORT0_MRCS3, val)

#define bfin_write_SPORT0_MTCS0 ( val   )     bfin_write32(SPORT0_MTCS0, val)

#define bfin_write_SPORT0_MTCS1 ( val   )     bfin_write32(SPORT0_MTCS1, val)

#define bfin_write_SPORT0_MTCS2 ( val   )     bfin_write32(SPORT0_MTCS2, val)

#define bfin_write_SPORT0_MTCS3 ( val   )     bfin_write32(SPORT0_MTCS3, val)

#define bfin_write_SPORT0_RCLKDIV ( val   )     bfin_write16(SPORT0_RCLKDIV, val)

#define bfin_write_SPORT0_RCR1 ( val   )     bfin_write16(SPORT0_RCR1, val)

#define bfin_write_SPORT0_RCR2 ( val   )     bfin_write16(SPORT0_RCR2, val)

#define bfin_write_SPORT0_RFSDIV ( val   )     bfin_write16(SPORT0_RFSDIV, val)

#define bfin_write_SPORT0_RX ( val   )     bfin_write32(SPORT0_RX, val)

#define bfin_write_SPORT0_STAT ( val   )     bfin_write16(SPORT0_STAT, val)

#define bfin_write_SPORT0_TCLKDIV ( val   )     bfin_write16(SPORT0_TCLKDIV, val)

#define bfin_write_SPORT0_TCR1 ( val   )     bfin_write16(SPORT0_TCR1, val)

#define bfin_write_SPORT0_TCR2 ( val   )     bfin_write16(SPORT0_TCR2, val)

#define bfin_write_SPORT0_TFSDIV ( val   )     bfin_write16(SPORT0_TFSDIV, val)

#define bfin_write_SPORT0_TX ( val   )     bfin_write32(SPORT0_TX, val)

#define bfin_write_SPORT1_CHNL ( val   )     bfin_write16(SPORT1_CHNL, val)

#define bfin_write_SPORT1_MCMC1 ( val   )     bfin_write16(SPORT1_MCMC1, val)

#define bfin_write_SPORT1_MCMC2 ( val   )     bfin_write16(SPORT1_MCMC2, val)

#define bfin_write_SPORT1_MRCS0 ( val   )     bfin_write32(SPORT1_MRCS0, val)

#define bfin_write_SPORT1_MRCS1 ( val   )     bfin_write32(SPORT1_MRCS1, val)

#define bfin_write_SPORT1_MRCS2 ( val   )     bfin_write32(SPORT1_MRCS2, val)

#define bfin_write_SPORT1_MRCS3 ( val   )     bfin_write32(SPORT1_MRCS3, val)

#define bfin_write_SPORT1_MTCS0 ( val   )     bfin_write32(SPORT1_MTCS0, val)

#define bfin_write_SPORT1_MTCS1 ( val   )     bfin_write32(SPORT1_MTCS1, val)

#define bfin_write_SPORT1_MTCS2 ( val   )     bfin_write32(SPORT1_MTCS2, val)

#define bfin_write_SPORT1_MTCS3 ( val   )     bfin_write32(SPORT1_MTCS3, val)

#define bfin_write_SPORT1_RCLKDIV ( val   )     bfin_write16(SPORT1_RCLKDIV, val)

#define bfin_write_SPORT1_RCR1 ( val   )     bfin_write16(SPORT1_RCR1, val)

#define bfin_write_SPORT1_RCR2 ( val   )     bfin_write16(SPORT1_RCR2, val)

#define bfin_write_SPORT1_RFSDIV ( val   )     bfin_write16(SPORT1_RFSDIV, val)

#define bfin_write_SPORT1_RX ( val   )     bfin_write32(SPORT1_RX, val)

#define bfin_write_SPORT1_STAT ( val   )     bfin_write16(SPORT1_STAT, val)

#define bfin_write_SPORT1_TCLKDIV ( val   )     bfin_write16(SPORT1_TCLKDIV, val)

#define bfin_write_SPORT1_TCR1 ( val   )     bfin_write16(SPORT1_TCR1, val)

#define bfin_write_SPORT1_TCR2 ( val   )     bfin_write16(SPORT1_TCR2, val)

#define bfin_write_SPORT1_TFSDIV ( val   )     bfin_write16(SPORT1_TFSDIV, val)

#define bfin_write_SPORT1_TX ( val   )     bfin_write32(SPORT1_TX, val)

#define bfin_write_TCNTL ( val   )     bfin_write32(TCNTL, val)

#define bfin_write_TCOUNT ( val   )     bfin_write32(TCOUNT, val)

#define bfin_write_TIMER0_CONFIG ( val   )     bfin_write16(TIMER0_CONFIG, val)

#define bfin_write_TIMER0_COUNTER ( val   )     bfin_write32(TIMER0_COUNTER, val)

#define bfin_write_TIMER0_PERIOD ( val   )     bfin_write32(TIMER0_PERIOD, val)

#define bfin_write_TIMER0_WIDTH ( val   )     bfin_write32(TIMER0_WIDTH, val)

#define bfin_write_TIMER10_CONFIG ( val   )     bfin_write16(TIMER10_CONFIG, val)

#define bfin_write_TIMER10_COUNTER ( val   )     bfin_write32(TIMER10_COUNTER, val)

#define bfin_write_TIMER10_PERIOD ( val   )     bfin_write32(TIMER10_PERIOD, val)

#define bfin_write_TIMER10_WIDTH ( val   )     bfin_write32(TIMER10_WIDTH, val)

#define bfin_write_TIMER11_CONFIG ( val   )     bfin_write16(TIMER11_CONFIG, val)

#define bfin_write_TIMER11_COUNTER ( val   )     bfin_write32(TIMER11_COUNTER, val)

#define bfin_write_TIMER11_PERIOD ( val   )     bfin_write32(TIMER11_PERIOD, val)

#define bfin_write_TIMER11_WIDTH ( val   )     bfin_write32(TIMER11_WIDTH, val)

#define bfin_write_TIMER1_CONFIG ( val   )     bfin_write16(TIMER1_CONFIG, val)

#define bfin_write_TIMER1_COUNTER ( val   )     bfin_write32(TIMER1_COUNTER, val)

#define bfin_write_TIMER1_PERIOD ( val   )     bfin_write32(TIMER1_PERIOD, val)

#define bfin_write_TIMER1_WIDTH ( val   )     bfin_write32(TIMER1_WIDTH, val)

#define bfin_write_TIMER2_CONFIG ( val   )     bfin_write16(TIMER2_CONFIG, val)

#define bfin_write_TIMER2_COUNTER ( val   )     bfin_write32(TIMER2_COUNTER, val)

#define bfin_write_TIMER2_PERIOD ( val   )     bfin_write32(TIMER2_PERIOD, val)

#define bfin_write_TIMER2_WIDTH ( val   )     bfin_write32(TIMER2_WIDTH, val)

#define bfin_write_TIMER3_CONFIG ( val   )     bfin_write16(TIMER3_CONFIG, val)

#define bfin_write_TIMER3_COUNTER ( val   )     bfin_write32(TIMER3_COUNTER, val)

#define bfin_write_TIMER3_PERIOD ( val   )     bfin_write32(TIMER3_PERIOD, val)

#define bfin_write_TIMER3_WIDTH ( val   )     bfin_write32(TIMER3_WIDTH, val)

#define bfin_write_TIMER4_CONFIG ( val   )     bfin_write16(TIMER4_CONFIG, val)

#define bfin_write_TIMER4_COUNTER ( val   )     bfin_write32(TIMER4_COUNTER, val)

#define bfin_write_TIMER4_PERIOD ( val   )     bfin_write32(TIMER4_PERIOD, val)

#define bfin_write_TIMER4_WIDTH ( val   )     bfin_write32(TIMER4_WIDTH, val)

#define bfin_write_TIMER5_CONFIG ( val   )     bfin_write16(TIMER5_CONFIG, val)

#define bfin_write_TIMER5_COUNTER ( val   )     bfin_write32(TIMER5_COUNTER, val)

#define bfin_write_TIMER5_PERIOD ( val   )     bfin_write32(TIMER5_PERIOD, val)

#define bfin_write_TIMER5_WIDTH ( val   )     bfin_write32(TIMER5_WIDTH, val)

#define bfin_write_TIMER6_CONFIG ( val   )     bfin_write16(TIMER6_CONFIG, val)

#define bfin_write_TIMER6_COUNTER ( val   )     bfin_write32(TIMER6_COUNTER, val)

#define bfin_write_TIMER6_PERIOD ( val   )     bfin_write32(TIMER6_PERIOD, val)

#define bfin_write_TIMER6_WIDTH ( val   )     bfin_write32(TIMER6_WIDTH, val)

#define bfin_write_TIMER7_CONFIG ( val   )     bfin_write16(TIMER7_CONFIG, val)

#define bfin_write_TIMER7_COUNTER ( val   )     bfin_write32(TIMER7_COUNTER, val)

#define bfin_write_TIMER7_PERIOD ( val   )     bfin_write32(TIMER7_PERIOD, val)

#define bfin_write_TIMER7_WIDTH ( val   )     bfin_write32(TIMER7_WIDTH, val)

#define bfin_write_TIMER8_CONFIG ( val   )     bfin_write16(TIMER8_CONFIG, val)

#define bfin_write_TIMER8_COUNTER ( val   )     bfin_write32(TIMER8_COUNTER, val)

#define bfin_write_TIMER8_PERIOD ( val   )     bfin_write32(TIMER8_PERIOD, val)

#define bfin_write_TIMER8_WIDTH ( val   )     bfin_write32(TIMER8_WIDTH, val)

#define bfin_write_TIMER9_CONFIG ( val   )     bfin_write16(TIMER9_CONFIG, val)

#define bfin_write_TIMER9_COUNTER ( val   )     bfin_write32(TIMER9_COUNTER, val)

#define bfin_write_TIMER9_PERIOD ( val   )     bfin_write32(TIMER9_PERIOD, val)

#define bfin_write_TIMER9_WIDTH ( val   )     bfin_write32(TIMER9_WIDTH, val)

#define bfin_write_TMRS4_DISABLE ( val   )     bfin_write32(TMRS4_DISABLE, val)

#define bfin_write_TMRS4_ENABLE ( val   )     bfin_write32(TMRS4_ENABLE, val)

#define bfin_write_TMRS4_STATUS ( val   )     bfin_write32(TMRS4_STATUS, val)

#define bfin_write_TMRS8_DISABLE ( val   )     bfin_write32(TMRS8_DISABLE, val)

#define bfin_write_TMRS8_ENABLE ( val   )     bfin_write32(TMRS8_ENABLE, val)

#define bfin_write_TMRS8_STATUS ( val   )     bfin_write32(TMRS8_STATUS, val)

#define bfin_write_TPERIOD ( val   )     bfin_write32(TPERIOD, val)

#define bfin_write_TSCALE ( val   )     bfin_write32(TSCALE, val)

#define bfin_write_VR_CTL ( val   )     bfin_write16(VR_CTL, val)

#define bfin_write_WDOGA_CNT ( val   )     bfin_write32(WDOGA_CNT, val)

#define bfin_write_WDOGA_CTL ( val   )     bfin_write16(WDOGA_CTL, val)

#define bfin_write_WDOGA_STAT ( val   )     bfin_write32(WDOGA_STAT, val)

#define bfin_write_WDOGB_CNT ( val   )     bfin_write32(WDOGB_CNT, val)

#define bfin_write_WDOGB_CTL ( val   )     bfin_write16(WDOGB_CTL, val)

#define bfin_write_WDOGB_STAT ( val   )     bfin_write32(WDOGB_STAT, val)

#define pCHIPID   ((uint32_t volatile *)CHIPID)

#define pDMA1_0_CONFIG   ((uint16_t volatile *)DMA1_0_CONFIG)

#define pDMA1_0_CURR_ADDR   ((void * volatile *)DMA1_0_CURR_ADDR)

#define pDMA1_0_CURR_DESC_PTR   ((void * volatile *)DMA1_0_CURR_DESC_PTR)

#define pDMA1_0_CURR_X_COUNT   ((uint16_t volatile *)DMA1_0_CURR_X_COUNT)

#define pDMA1_0_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT)

#define pDMA1_0_IRQ_STATUS   ((uint16_t volatile *)DMA1_0_IRQ_STATUS)

#define pDMA1_0_NEXT_DESC_PTR   ((void * volatile *)DMA1_0_NEXT_DESC_PTR)

#define pDMA1_0_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP)

#define pDMA1_0_START_ADDR   ((void * volatile *)DMA1_0_START_ADDR)

#define pDMA1_0_X_COUNT   ((uint16_t volatile *)DMA1_0_X_COUNT)

#define pDMA1_0_X_MODIFY   ((uint16_t volatile *)DMA1_0_X_MODIFY)

#define pDMA1_0_Y_COUNT   ((uint16_t volatile *)DMA1_0_Y_COUNT)

#define pDMA1_0_Y_MODIFY   ((uint16_t volatile *)DMA1_0_Y_MODIFY)

#define pDMA1_10_CONFIG   ((uint16_t volatile *)DMA1_10_CONFIG)

#define pDMA1_10_CURR_ADDR   ((void * volatile *)DMA1_10_CURR_ADDR)

#define pDMA1_10_CURR_DESC_PTR   ((void * volatile *)DMA1_10_CURR_DESC_PTR)

#define pDMA1_10_CURR_X_COUNT   ((uint16_t volatile *)DMA1_10_CURR_X_COUNT)

#define pDMA1_10_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT)

#define pDMA1_10_IRQ_STATUS   ((uint16_t volatile *)DMA1_10_IRQ_STATUS)

#define pDMA1_10_NEXT_DESC_PTR   ((void * volatile *)DMA1_10_NEXT_DESC_PTR)

#define pDMA1_10_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP)

#define pDMA1_10_START_ADDR   ((void * volatile *)DMA1_10_START_ADDR)

#define pDMA1_10_X_COUNT   ((uint16_t volatile *)DMA1_10_X_COUNT)

#define pDMA1_10_X_MODIFY   ((uint16_t volatile *)DMA1_10_X_MODIFY)

#define pDMA1_10_Y_COUNT   ((uint16_t volatile *)DMA1_10_Y_COUNT)

#define pDMA1_10_Y_MODIFY   ((uint16_t volatile *)DMA1_10_Y_MODIFY)

#define pDMA1_11_CONFIG   ((uint16_t volatile *)DMA1_11_CONFIG)

#define pDMA1_11_CURR_ADDR   ((void * volatile *)DMA1_11_CURR_ADDR)

#define pDMA1_11_CURR_DESC_PTR   ((void * volatile *)DMA1_11_CURR_DESC_PTR)

#define pDMA1_11_CURR_X_COUNT   ((uint16_t volatile *)DMA1_11_CURR_X_COUNT)

#define pDMA1_11_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT)

#define pDMA1_11_IRQ_STATUS   ((uint16_t volatile *)DMA1_11_IRQ_STATUS)

#define pDMA1_11_NEXT_DESC_PTR   ((void * volatile *)DMA1_11_NEXT_DESC_PTR)

#define pDMA1_11_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP)

#define pDMA1_11_START_ADDR   ((void * volatile *)DMA1_11_START_ADDR)

#define pDMA1_11_X_COUNT   ((uint16_t volatile *)DMA1_11_X_COUNT)

#define pDMA1_11_X_MODIFY   ((uint16_t volatile *)DMA1_11_X_MODIFY)

#define pDMA1_11_Y_COUNT   ((uint16_t volatile *)DMA1_11_Y_COUNT)

#define pDMA1_11_Y_MODIFY   ((uint16_t volatile *)DMA1_11_Y_MODIFY)

#define pDMA1_1_CONFIG   ((uint16_t volatile *)DMA1_1_CONFIG)

#define pDMA1_1_CURR_ADDR   ((void * volatile *)DMA1_1_CURR_ADDR)

#define pDMA1_1_CURR_DESC_PTR   ((void * volatile *)DMA1_1_CURR_DESC_PTR)

#define pDMA1_1_CURR_X_COUNT   ((uint16_t volatile *)DMA1_1_CURR_X_COUNT)

#define pDMA1_1_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT)

#define pDMA1_1_IRQ_STATUS   ((uint16_t volatile *)DMA1_1_IRQ_STATUS)

#define pDMA1_1_NEXT_DESC_PTR   ((void * volatile *)DMA1_1_NEXT_DESC_PTR)

#define pDMA1_1_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP)

#define pDMA1_1_START_ADDR   ((void * volatile *)DMA1_1_START_ADDR)

#define pDMA1_1_X_COUNT   ((uint16_t volatile *)DMA1_1_X_COUNT)

#define pDMA1_1_X_MODIFY   ((uint16_t volatile *)DMA1_1_X_MODIFY)

#define pDMA1_1_Y_COUNT   ((uint16_t volatile *)DMA1_1_Y_COUNT)

#define pDMA1_1_Y_MODIFY   ((uint16_t volatile *)DMA1_1_Y_MODIFY)

#define pDMA1_2_CONFIG   ((uint16_t volatile *)DMA1_2_CONFIG)

#define pDMA1_2_CURR_ADDR   ((void * volatile *)DMA1_2_CURR_ADDR)

#define pDMA1_2_CURR_DESC_PTR   ((void * volatile *)DMA1_2_CURR_DESC_PTR)

#define pDMA1_2_CURR_X_COUNT   ((uint16_t volatile *)DMA1_2_CURR_X_COUNT)

#define pDMA1_2_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT)

#define pDMA1_2_IRQ_STATUS   ((uint16_t volatile *)DMA1_2_IRQ_STATUS)

#define pDMA1_2_NEXT_DESC_PTR   ((void * volatile *)DMA1_2_NEXT_DESC_PTR)

#define pDMA1_2_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP)

#define pDMA1_2_START_ADDR   ((void * volatile *)DMA1_2_START_ADDR)

#define pDMA1_2_X_COUNT   ((uint16_t volatile *)DMA1_2_X_COUNT)

#define pDMA1_2_X_MODIFY   ((uint16_t volatile *)DMA1_2_X_MODIFY)

#define pDMA1_2_Y_COUNT   ((uint16_t volatile *)DMA1_2_Y_COUNT)

#define pDMA1_2_Y_MODIFY   ((uint16_t volatile *)DMA1_2_Y_MODIFY)

#define pDMA1_3_CONFIG   ((uint16_t volatile *)DMA1_3_CONFIG)

#define pDMA1_3_CURR_ADDR   ((void * volatile *)DMA1_3_CURR_ADDR)

#define pDMA1_3_CURR_DESC_PTR   ((void * volatile *)DMA1_3_CURR_DESC_PTR)

#define pDMA1_3_CURR_X_COUNT   ((uint16_t volatile *)DMA1_3_CURR_X_COUNT)

#define pDMA1_3_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT)

#define pDMA1_3_IRQ_STATUS   ((uint16_t volatile *)DMA1_3_IRQ_STATUS)

#define pDMA1_3_NEXT_DESC_PTR   ((void * volatile *)DMA1_3_NEXT_DESC_PTR)

#define pDMA1_3_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP)

#define pDMA1_3_START_ADDR   ((void * volatile *)DMA1_3_START_ADDR)

#define pDMA1_3_X_COUNT   ((uint16_t volatile *)DMA1_3_X_COUNT)

#define pDMA1_3_X_MODIFY   ((uint16_t volatile *)DMA1_3_X_MODIFY)

#define pDMA1_3_Y_COUNT   ((uint16_t volatile *)DMA1_3_Y_COUNT)

#define pDMA1_3_Y_MODIFY   ((uint16_t volatile *)DMA1_3_Y_MODIFY)

#define pDMA1_4_CONFIG   ((uint16_t volatile *)DMA1_4_CONFIG)

#define pDMA1_4_CURR_ADDR   ((void * volatile *)DMA1_4_CURR_ADDR)

#define pDMA1_4_CURR_DESC_PTR   ((void * volatile *)DMA1_4_CURR_DESC_PTR)

#define pDMA1_4_CURR_X_COUNT   ((uint16_t volatile *)DMA1_4_CURR_X_COUNT)

#define pDMA1_4_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT)

#define pDMA1_4_IRQ_STATUS   ((uint16_t volatile *)DMA1_4_IRQ_STATUS)

#define pDMA1_4_NEXT_DESC_PTR   ((void * volatile *)DMA1_4_NEXT_DESC_PTR)

#define pDMA1_4_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP)

#define pDMA1_4_START_ADDR   ((void * volatile *)DMA1_4_START_ADDR)

#define pDMA1_4_X_COUNT   ((uint16_t volatile *)DMA1_4_X_COUNT)

#define pDMA1_4_X_MODIFY   ((uint16_t volatile *)DMA1_4_X_MODIFY)

#define pDMA1_4_Y_COUNT   ((uint16_t volatile *)DMA1_4_Y_COUNT)

#define pDMA1_4_Y_MODIFY   ((uint16_t volatile *)DMA1_4_Y_MODIFY)

#define pDMA1_5_CONFIG   ((uint16_t volatile *)DMA1_5_CONFIG)

#define pDMA1_5_CURR_ADDR   ((void * volatile *)DMA1_5_CURR_ADDR)

#define pDMA1_5_CURR_DESC_PTR   ((void * volatile *)DMA1_5_CURR_DESC_PTR)

#define pDMA1_5_CURR_X_COUNT   ((uint16_t volatile *)DMA1_5_CURR_X_COUNT)

#define pDMA1_5_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT)

#define pDMA1_5_IRQ_STATUS   ((uint16_t volatile *)DMA1_5_IRQ_STATUS)

#define pDMA1_5_NEXT_DESC_PTR   ((void * volatile *)DMA1_5_NEXT_DESC_PTR)

#define pDMA1_5_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP)

#define pDMA1_5_START_ADDR   ((void * volatile *)DMA1_5_START_ADDR)

#define pDMA1_5_X_COUNT   ((uint16_t volatile *)DMA1_5_X_COUNT)

#define pDMA1_5_X_MODIFY   ((uint16_t volatile *)DMA1_5_X_MODIFY)

#define pDMA1_5_Y_COUNT   ((uint16_t volatile *)DMA1_5_Y_COUNT)

#define pDMA1_5_Y_MODIFY   ((uint16_t volatile *)DMA1_5_Y_MODIFY)

#define pDMA1_6_CONFIG   ((uint16_t volatile *)DMA1_6_CONFIG)

#define pDMA1_6_CURR_ADDR   ((void * volatile *)DMA1_6_CURR_ADDR)

#define pDMA1_6_CURR_DESC_PTR   ((void * volatile *)DMA1_6_CURR_DESC_PTR)

#define pDMA1_6_CURR_X_COUNT   ((uint16_t volatile *)DMA1_6_CURR_X_COUNT)

#define pDMA1_6_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT)

#define pDMA1_6_IRQ_STATUS   ((uint16_t volatile *)DMA1_6_IRQ_STATUS)

#define pDMA1_6_NEXT_DESC_PTR   ((void * volatile *)DMA1_6_NEXT_DESC_PTR)

#define pDMA1_6_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP)

#define pDMA1_6_START_ADDR   ((void * volatile *)DMA1_6_START_ADDR)

#define pDMA1_6_X_COUNT   ((uint16_t volatile *)DMA1_6_X_COUNT)

#define pDMA1_6_X_MODIFY   ((uint16_t volatile *)DMA1_6_X_MODIFY)

#define pDMA1_6_Y_COUNT   ((uint16_t volatile *)DMA1_6_Y_COUNT)

#define pDMA1_6_Y_MODIFY   ((uint16_t volatile *)DMA1_6_Y_MODIFY)

#define pDMA1_7_CONFIG   ((uint16_t volatile *)DMA1_7_CONFIG)

#define pDMA1_7_CURR_ADDR   ((void * volatile *)DMA1_7_CURR_ADDR)

#define pDMA1_7_CURR_DESC_PTR   ((void * volatile *)DMA1_7_CURR_DESC_PTR)

#define pDMA1_7_CURR_X_COUNT   ((uint16_t volatile *)DMA1_7_CURR_X_COUNT)

#define pDMA1_7_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT)

#define pDMA1_7_IRQ_STATUS   ((uint16_t volatile *)DMA1_7_IRQ_STATUS)

#define pDMA1_7_NEXT_DESC_PTR   ((void * volatile *)DMA1_7_NEXT_DESC_PTR)

#define pDMA1_7_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP)

#define pDMA1_7_START_ADDR   ((void * volatile *)DMA1_7_START_ADDR)

#define pDMA1_7_X_COUNT   ((uint16_t volatile *)DMA1_7_X_COUNT)

#define pDMA1_7_X_MODIFY   ((uint16_t volatile *)DMA1_7_X_MODIFY)

#define pDMA1_7_Y_COUNT   ((uint16_t volatile *)DMA1_7_Y_COUNT)

#define pDMA1_7_Y_MODIFY   ((uint16_t volatile *)DMA1_7_Y_MODIFY)

#define pDMA1_8_CONFIG   ((uint16_t volatile *)DMA1_8_CONFIG)

#define pDMA1_8_CURR_ADDR   ((void * volatile *)DMA1_8_CURR_ADDR)

#define pDMA1_8_CURR_DESC_PTR   ((void * volatile *)DMA1_8_CURR_DESC_PTR)

#define pDMA1_8_CURR_X_COUNT   ((uint16_t volatile *)DMA1_8_CURR_X_COUNT)

#define pDMA1_8_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT)

#define pDMA1_8_IRQ_STATUS   ((uint16_t volatile *)DMA1_8_IRQ_STATUS)

#define pDMA1_8_NEXT_DESC_PTR   ((void * volatile *)DMA1_8_NEXT_DESC_PTR)

#define pDMA1_8_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP)

#define pDMA1_8_START_ADDR   ((void * volatile *)DMA1_8_START_ADDR)

#define pDMA1_8_X_COUNT   ((uint16_t volatile *)DMA1_8_X_COUNT)

#define pDMA1_8_X_MODIFY   ((uint16_t volatile *)DMA1_8_X_MODIFY)

#define pDMA1_8_Y_COUNT   ((uint16_t volatile *)DMA1_8_Y_COUNT)

#define pDMA1_8_Y_MODIFY   ((uint16_t volatile *)DMA1_8_Y_MODIFY)

#define pDMA1_9_CONFIG   ((uint16_t volatile *)DMA1_9_CONFIG)

#define pDMA1_9_CURR_ADDR   ((void * volatile *)DMA1_9_CURR_ADDR)

#define pDMA1_9_CURR_DESC_PTR   ((void * volatile *)DMA1_9_CURR_DESC_PTR)

#define pDMA1_9_CURR_X_COUNT   ((uint16_t volatile *)DMA1_9_CURR_X_COUNT)

#define pDMA1_9_CURR_Y_COUNT   ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT)

#define pDMA1_9_IRQ_STATUS   ((uint16_t volatile *)DMA1_9_IRQ_STATUS)

#define pDMA1_9_NEXT_DESC_PTR   ((void * volatile *)DMA1_9_NEXT_DESC_PTR)

#define pDMA1_9_PERIPHERAL_MAP   ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP)

#define pDMA1_9_START_ADDR   ((void * volatile *)DMA1_9_START_ADDR)

#define pDMA1_9_X_COUNT   ((uint16_t volatile *)DMA1_9_X_COUNT)

#define pDMA1_9_X_MODIFY   ((uint16_t volatile *)DMA1_9_X_MODIFY)

#define pDMA1_9_Y_COUNT   ((uint16_t volatile *)DMA1_9_Y_COUNT)

#define pDMA1_9_Y_MODIFY   ((uint16_t volatile *)DMA1_9_Y_MODIFY)

#define pDMA1_TC_CNT   ((uint16_t volatile *)DMA1_TC_CNT)

#define pDMA1_TC_PER   ((uint16_t volatile *)DMA1_TC_PER)

#define pDMA2_0_CONFIG   ((uint16_t volatile *)DMA2_0_CONFIG)

#define pDMA2_0_CURR_ADDR   ((void * volatile *)DMA2_0_CURR_ADDR)

#define pDMA2_0_CURR_DESC_PTR   ((void * volatile *)DMA2_0_CURR_DESC_PTR)

#define pDMA2_0_CURR_X_COUNT   ((uint16_t volatile *)DMA2_0_CURR_X_COUNT)

#define pDMA2_0_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT)

#define pDMA2_0_IRQ_STATUS   ((uint16_t volatile *)DMA2_0_IRQ_STATUS)

#define pDMA2_0_NEXT_DESC_PTR   ((void * volatile *)DMA2_0_NEXT_DESC_PTR)

#define pDMA2_0_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP)

#define pDMA2_0_START_ADDR   ((void * volatile *)DMA2_0_START_ADDR)

#define pDMA2_0_X_COUNT   ((uint16_t volatile *)DMA2_0_X_COUNT)

#define pDMA2_0_X_MODIFY   ((uint16_t volatile *)DMA2_0_X_MODIFY)

#define pDMA2_0_Y_COUNT   ((uint16_t volatile *)DMA2_0_Y_COUNT)

#define pDMA2_0_Y_MODIFY   ((uint16_t volatile *)DMA2_0_Y_MODIFY)

#define pDMA2_10_CONFIG   ((uint16_t volatile *)DMA2_10_CONFIG)

#define pDMA2_10_CURR_ADDR   ((void * volatile *)DMA2_10_CURR_ADDR)

#define pDMA2_10_CURR_DESC_PTR   ((void * volatile *)DMA2_10_CURR_DESC_PTR)

#define pDMA2_10_CURR_X_COUNT   ((uint16_t volatile *)DMA2_10_CURR_X_COUNT)

#define pDMA2_10_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT)

#define pDMA2_10_IRQ_STATUS   ((uint16_t volatile *)DMA2_10_IRQ_STATUS)

#define pDMA2_10_NEXT_DESC_PTR   ((void * volatile *)DMA2_10_NEXT_DESC_PTR)

#define pDMA2_10_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP)

#define pDMA2_10_START_ADDR   ((void * volatile *)DMA2_10_START_ADDR)

#define pDMA2_10_X_COUNT   ((uint16_t volatile *)DMA2_10_X_COUNT)

#define pDMA2_10_X_MODIFY   ((uint16_t volatile *)DMA2_10_X_MODIFY)

#define pDMA2_10_Y_COUNT   ((uint16_t volatile *)DMA2_10_Y_COUNT)

#define pDMA2_10_Y_MODIFY   ((uint16_t volatile *)DMA2_10_Y_MODIFY)

#define pDMA2_11_CONFIG   ((uint16_t volatile *)DMA2_11_CONFIG)

#define pDMA2_11_CURR_ADDR   ((void * volatile *)DMA2_11_CURR_ADDR)

#define pDMA2_11_CURR_DESC_PTR   ((void * volatile *)DMA2_11_CURR_DESC_PTR)

#define pDMA2_11_CURR_X_COUNT   ((uint16_t volatile *)DMA2_11_CURR_X_COUNT)

#define pDMA2_11_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT)

#define pDMA2_11_IRQ_STATUS   ((uint16_t volatile *)DMA2_11_IRQ_STATUS)

#define pDMA2_11_NEXT_DESC_PTR   ((void * volatile *)DMA2_11_NEXT_DESC_PTR)

#define pDMA2_11_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP)

#define pDMA2_11_START_ADDR   ((void * volatile *)DMA2_11_START_ADDR)

#define pDMA2_11_X_COUNT   ((uint16_t volatile *)DMA2_11_X_COUNT)

#define pDMA2_11_X_MODIFY   ((uint16_t volatile *)DMA2_11_X_MODIFY)

#define pDMA2_11_Y_COUNT   ((uint16_t volatile *)DMA2_11_Y_COUNT)

#define pDMA2_11_Y_MODIFY   ((uint16_t volatile *)DMA2_11_Y_MODIFY)

#define pDMA2_1_CONFIG   ((uint16_t volatile *)DMA2_1_CONFIG)

#define pDMA2_1_CURR_ADDR   ((void * volatile *)DMA2_1_CURR_ADDR)

#define pDMA2_1_CURR_DESC_PTR   ((void * volatile *)DMA2_1_CURR_DESC_PTR)

#define pDMA2_1_CURR_X_COUNT   ((uint16_t volatile *)DMA2_1_CURR_X_COUNT)

#define pDMA2_1_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT)

#define pDMA2_1_IRQ_STATUS   ((uint16_t volatile *)DMA2_1_IRQ_STATUS)

#define pDMA2_1_NEXT_DESC_PTR   ((void * volatile *)DMA2_1_NEXT_DESC_PTR)

#define pDMA2_1_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP)

#define pDMA2_1_START_ADDR   ((void * volatile *)DMA2_1_START_ADDR)

#define pDMA2_1_X_COUNT   ((uint16_t volatile *)DMA2_1_X_COUNT)

#define pDMA2_1_X_MODIFY   ((uint16_t volatile *)DMA2_1_X_MODIFY)

#define pDMA2_1_Y_COUNT   ((uint16_t volatile *)DMA2_1_Y_COUNT)

#define pDMA2_1_Y_MODIFY   ((uint16_t volatile *)DMA2_1_Y_MODIFY)

#define pDMA2_2_CONFIG   ((uint16_t volatile *)DMA2_2_CONFIG)

#define pDMA2_2_CURR_ADDR   ((void * volatile *)DMA2_2_CURR_ADDR)

#define pDMA2_2_CURR_DESC_PTR   ((void * volatile *)DMA2_2_CURR_DESC_PTR)

#define pDMA2_2_CURR_X_COUNT   ((uint16_t volatile *)DMA2_2_CURR_X_COUNT)

#define pDMA2_2_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT)

#define pDMA2_2_IRQ_STATUS   ((uint16_t volatile *)DMA2_2_IRQ_STATUS)

#define pDMA2_2_NEXT_DESC_PTR   ((void * volatile *)DMA2_2_NEXT_DESC_PTR)

#define pDMA2_2_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP)

#define pDMA2_2_START_ADDR   ((void * volatile *)DMA2_2_START_ADDR)

#define pDMA2_2_X_COUNT   ((uint16_t volatile *)DMA2_2_X_COUNT)

#define pDMA2_2_X_MODIFY   ((uint16_t volatile *)DMA2_2_X_MODIFY)

#define pDMA2_2_Y_COUNT   ((uint16_t volatile *)DMA2_2_Y_COUNT)

#define pDMA2_2_Y_MODIFY   ((uint16_t volatile *)DMA2_2_Y_MODIFY)

#define pDMA2_3_CONFIG   ((uint16_t volatile *)DMA2_3_CONFIG)

#define pDMA2_3_CURR_ADDR   ((void * volatile *)DMA2_3_CURR_ADDR)

#define pDMA2_3_CURR_DESC_PTR   ((void * volatile *)DMA2_3_CURR_DESC_PTR)

#define pDMA2_3_CURR_X_COUNT   ((uint16_t volatile *)DMA2_3_CURR_X_COUNT)

#define pDMA2_3_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT)

#define pDMA2_3_IRQ_STATUS   ((uint16_t volatile *)DMA2_3_IRQ_STATUS)

#define pDMA2_3_NEXT_DESC_PTR   ((void * volatile *)DMA2_3_NEXT_DESC_PTR)

#define pDMA2_3_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP)

#define pDMA2_3_START_ADDR   ((void * volatile *)DMA2_3_START_ADDR)

#define pDMA2_3_X_COUNT   ((uint16_t volatile *)DMA2_3_X_COUNT)

#define pDMA2_3_X_MODIFY   ((uint16_t volatile *)DMA2_3_X_MODIFY)

#define pDMA2_3_Y_COUNT   ((uint16_t volatile *)DMA2_3_Y_COUNT)

#define pDMA2_3_Y_MODIFY   ((uint16_t volatile *)DMA2_3_Y_MODIFY)

#define pDMA2_4_CONFIG   ((uint16_t volatile *)DMA2_4_CONFIG)

#define pDMA2_4_CURR_ADDR   ((void * volatile *)DMA2_4_CURR_ADDR)

#define pDMA2_4_CURR_DESC_PTR   ((void * volatile *)DMA2_4_CURR_DESC_PTR)

#define pDMA2_4_CURR_X_COUNT   ((uint16_t volatile *)DMA2_4_CURR_X_COUNT)

#define pDMA2_4_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT)

#define pDMA2_4_IRQ_STATUS   ((uint16_t volatile *)DMA2_4_IRQ_STATUS)

#define pDMA2_4_NEXT_DESC_PTR   ((void * volatile *)DMA2_4_NEXT_DESC_PTR)

#define pDMA2_4_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP)

#define pDMA2_4_START_ADDR   ((void * volatile *)DMA2_4_START_ADDR)

#define pDMA2_4_X_COUNT   ((uint16_t volatile *)DMA2_4_X_COUNT)

#define pDMA2_4_X_MODIFY   ((uint16_t volatile *)DMA2_4_X_MODIFY)

#define pDMA2_4_Y_COUNT   ((uint16_t volatile *)DMA2_4_Y_COUNT)

#define pDMA2_4_Y_MODIFY   ((uint16_t volatile *)DMA2_4_Y_MODIFY)

#define pDMA2_5_CONFIG   ((uint16_t volatile *)DMA2_5_CONFIG)

#define pDMA2_5_CURR_ADDR   ((void * volatile *)DMA2_5_CURR_ADDR)

#define pDMA2_5_CURR_DESC_PTR   ((void * volatile *)DMA2_5_CURR_DESC_PTR)

#define pDMA2_5_CURR_X_COUNT   ((uint16_t volatile *)DMA2_5_CURR_X_COUNT)

#define pDMA2_5_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT)

#define pDMA2_5_IRQ_STATUS   ((uint16_t volatile *)DMA2_5_IRQ_STATUS)

#define pDMA2_5_NEXT_DESC_PTR   ((void * volatile *)DMA2_5_NEXT_DESC_PTR)

#define pDMA2_5_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP)

#define pDMA2_5_START_ADDR   ((void * volatile *)DMA2_5_START_ADDR)

#define pDMA2_5_X_COUNT   ((uint16_t volatile *)DMA2_5_X_COUNT)

#define pDMA2_5_X_MODIFY   ((uint16_t volatile *)DMA2_5_X_MODIFY)

#define pDMA2_5_Y_COUNT   ((uint16_t volatile *)DMA2_5_Y_COUNT)

#define pDMA2_5_Y_MODIFY   ((uint16_t volatile *)DMA2_5_Y_MODIFY)

#define pDMA2_6_CONFIG   ((uint16_t volatile *)DMA2_6_CONFIG)

#define pDMA2_6_CURR_ADDR   ((void * volatile *)DMA2_6_CURR_ADDR)

#define pDMA2_6_CURR_DESC_PTR   ((void * volatile *)DMA2_6_CURR_DESC_PTR)

#define pDMA2_6_CURR_X_COUNT   ((uint16_t volatile *)DMA2_6_CURR_X_COUNT)

#define pDMA2_6_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT)

#define pDMA2_6_IRQ_STATUS   ((uint16_t volatile *)DMA2_6_IRQ_STATUS)

#define pDMA2_6_NEXT_DESC_PTR   ((void * volatile *)DMA2_6_NEXT_DESC_PTR)

#define pDMA2_6_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP)

#define pDMA2_6_START_ADDR   ((void * volatile *)DMA2_6_START_ADDR)

#define pDMA2_6_X_COUNT   ((uint16_t volatile *)DMA2_6_X_COUNT)

#define pDMA2_6_X_MODIFY   ((uint16_t volatile *)DMA2_6_X_MODIFY)

#define pDMA2_6_Y_COUNT   ((uint16_t volatile *)DMA2_6_Y_COUNT)

#define pDMA2_6_Y_MODIFY   ((uint16_t volatile *)DMA2_6_Y_MODIFY)

#define pDMA2_7_CONFIG   ((uint16_t volatile *)DMA2_7_CONFIG)

#define pDMA2_7_CURR_ADDR   ((void * volatile *)DMA2_7_CURR_ADDR)

#define pDMA2_7_CURR_DESC_PTR   ((void * volatile *)DMA2_7_CURR_DESC_PTR)

#define pDMA2_7_CURR_X_COUNT   ((uint16_t volatile *)DMA2_7_CURR_X_COUNT)

#define pDMA2_7_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT)

#define pDMA2_7_IRQ_STATUS   ((uint16_t volatile *)DMA2_7_IRQ_STATUS)

#define pDMA2_7_NEXT_DESC_PTR   ((void * volatile *)DMA2_7_NEXT_DESC_PTR)

#define pDMA2_7_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP)

#define pDMA2_7_START_ADDR   ((void * volatile *)DMA2_7_START_ADDR)

#define pDMA2_7_X_COUNT   ((uint16_t volatile *)DMA2_7_X_COUNT)

#define pDMA2_7_X_MODIFY   ((uint16_t volatile *)DMA2_7_X_MODIFY)

#define pDMA2_7_Y_COUNT   ((uint16_t volatile *)DMA2_7_Y_COUNT)

#define pDMA2_7_Y_MODIFY   ((uint16_t volatile *)DMA2_7_Y_MODIFY)

#define pDMA2_8_CONFIG   ((uint16_t volatile *)DMA2_8_CONFIG)

#define pDMA2_8_CURR_ADDR   ((void * volatile *)DMA2_8_CURR_ADDR)

#define pDMA2_8_CURR_DESC_PTR   ((void * volatile *)DMA2_8_CURR_DESC_PTR)

#define pDMA2_8_CURR_X_COUNT   ((uint16_t volatile *)DMA2_8_CURR_X_COUNT)

#define pDMA2_8_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT)

#define pDMA2_8_IRQ_STATUS   ((uint16_t volatile *)DMA2_8_IRQ_STATUS)

#define pDMA2_8_NEXT_DESC_PTR   ((void * volatile *)DMA2_8_NEXT_DESC_PTR)

#define pDMA2_8_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP)

#define pDMA2_8_START_ADDR   ((void * volatile *)DMA2_8_START_ADDR)

#define pDMA2_8_X_COUNT   ((uint16_t volatile *)DMA2_8_X_COUNT)

#define pDMA2_8_X_MODIFY   ((uint16_t volatile *)DMA2_8_X_MODIFY)

#define pDMA2_8_Y_COUNT   ((uint16_t volatile *)DMA2_8_Y_COUNT)

#define pDMA2_8_Y_MODIFY   ((uint16_t volatile *)DMA2_8_Y_MODIFY)

#define pDMA2_9_CONFIG   ((uint16_t volatile *)DMA2_9_CONFIG)

#define pDMA2_9_CURR_ADDR   ((void * volatile *)DMA2_9_CURR_ADDR)

#define pDMA2_9_CURR_DESC_PTR   ((void * volatile *)DMA2_9_CURR_DESC_PTR)

#define pDMA2_9_CURR_X_COUNT   ((uint16_t volatile *)DMA2_9_CURR_X_COUNT)

#define pDMA2_9_CURR_Y_COUNT   ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT)

#define pDMA2_9_IRQ_STATUS   ((uint16_t volatile *)DMA2_9_IRQ_STATUS)

#define pDMA2_9_NEXT_DESC_PTR   ((void * volatile *)DMA2_9_NEXT_DESC_PTR)

#define pDMA2_9_PERIPHERAL_MAP   ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP)

#define pDMA2_9_START_ADDR   ((void * volatile *)DMA2_9_START_ADDR)

#define pDMA2_9_X_COUNT   ((uint16_t volatile *)DMA2_9_X_COUNT)

#define pDMA2_9_X_MODIFY   ((uint16_t volatile *)DMA2_9_X_MODIFY)

#define pDMA2_9_Y_COUNT   ((uint16_t volatile *)DMA2_9_Y_COUNT)

#define pDMA2_9_Y_MODIFY   ((uint16_t volatile *)DMA2_9_Y_MODIFY)

#define pDMA2_TC_CNT   ((uint16_t volatile *)DMA2_TC_CNT)

#define pDMA2_TC_PER   ((uint16_t volatile *)DMA2_TC_PER)

#define pEVT0   ((void * volatile *)EVT0)

#define pEVT1   ((void * volatile *)EVT1)

#define pEVT10   ((void * volatile *)EVT10)

#define pEVT11   ((void * volatile *)EVT11)

#define pEVT12   ((void * volatile *)EVT12)

#define pEVT13   ((void * volatile *)EVT13)

#define pEVT14   ((void * volatile *)EVT14)

#define pEVT15   ((void * volatile *)EVT15)

#define pEVT2   ((void * volatile *)EVT2)

#define pEVT3   ((void * volatile *)EVT3)

#define pEVT4   ((void * volatile *)EVT4)

#define pEVT5   ((void * volatile *)EVT5)

#define pEVT6   ((void * volatile *)EVT6)

#define pEVT7   ((void * volatile *)EVT7)

#define pEVT8   ((void * volatile *)EVT8)

#define pEVT9   ((void * volatile *)EVT9)

#define pFIO0_BOTH   ((uint16_t volatile *)FIO0_BOTH)

#define pFIO0_DIR   ((uint16_t volatile *)FIO0_DIR)

#define pFIO0_EDGE   ((uint16_t volatile *)FIO0_EDGE)

#define pFIO0_FLAG_C   ((uint16_t volatile *)FIO0_FLAG_C)

#define pFIO0_FLAG_D   ((uint16_t volatile *)FIO0_FLAG_D)

#define pFIO0_FLAG_S   ((uint16_t volatile *)FIO0_FLAG_S)

#define pFIO0_FLAG_T   ((uint16_t volatile *)FIO0_FLAG_T)

#define pFIO0_INEN   ((uint16_t volatile *)FIO0_INEN)

#define pFIO0_MASKA_C   ((uint16_t volatile *)FIO0_MASKA_C)

#define pFIO0_MASKA_D   ((uint16_t volatile *)FIO0_MASKA_D)

#define pFIO0_MASKA_S   ((uint16_t volatile *)FIO0_MASKA_S)

#define pFIO0_MASKA_T   ((uint16_t volatile *)FIO0_MASKA_T)

#define pFIO0_MASKB_C   ((uint16_t volatile *)FIO0_MASKB_C)

#define pFIO0_MASKB_D   ((uint16_t volatile *)FIO0_MASKB_D)

#define pFIO0_MASKB_S   ((uint16_t volatile *)FIO0_MASKB_S)

#define pFIO0_MASKB_T   ((uint16_t volatile *)FIO0_MASKB_T)

#define pFIO0_POLAR   ((uint16_t volatile *)FIO0_POLAR)

#define pFIO1_BOTH   ((uint16_t volatile *)FIO1_BOTH)

#define pFIO1_DIR   ((uint16_t volatile *)FIO1_DIR)

#define pFIO1_EDGE   ((uint16_t volatile *)FIO1_EDGE)

#define pFIO1_FLAG_C   ((uint16_t volatile *)FIO1_FLAG_C)

#define pFIO1_FLAG_D   ((uint16_t volatile *)FIO1_FLAG_D)

#define pFIO1_FLAG_S   ((uint16_t volatile *)FIO1_FLAG_S)

#define pFIO1_FLAG_T   ((uint16_t volatile *)FIO1_FLAG_T)

#define pFIO1_INEN   ((uint16_t volatile *)FIO1_INEN)

#define pFIO1_MASKA_C   ((uint16_t volatile *)FIO1_MASKA_C)

#define pFIO1_MASKA_D   ((uint16_t volatile *)FIO1_MASKA_D)

#define pFIO1_MASKA_S   ((uint16_t volatile *)FIO1_MASKA_S)

#define pFIO1_MASKA_T   ((uint16_t volatile *)FIO1_MASKA_T)

#define pFIO1_MASKB_C   ((uint16_t volatile *)FIO1_MASKB_C)

#define pFIO1_MASKB_D   ((uint16_t volatile *)FIO1_MASKB_D)

#define pFIO1_MASKB_S   ((uint16_t volatile *)FIO1_MASKB_S)

#define pFIO1_MASKB_T   ((uint16_t volatile *)FIO1_MASKB_T)

#define pFIO1_POLAR   ((uint16_t volatile *)FIO1_POLAR)

#define pFIO2_BOTH   ((uint16_t volatile *)FIO2_BOTH)

#define pFIO2_DIR   ((uint16_t volatile *)FIO2_DIR)

#define pFIO2_EDGE   ((uint16_t volatile *)FIO2_EDGE)

#define pFIO2_FLAG_C   ((uint16_t volatile *)FIO2_FLAG_C)

#define pFIO2_FLAG_D   ((uint16_t volatile *)FIO2_FLAG_D)

#define pFIO2_FLAG_S   ((uint16_t volatile *)FIO2_FLAG_S)

#define pFIO2_FLAG_T   ((uint16_t volatile *)FIO2_FLAG_T)

#define pFIO2_INEN   ((uint16_t volatile *)FIO2_INEN)

#define pFIO2_MASKA_C   ((uint16_t volatile *)FIO2_MASKA_C)

#define pFIO2_MASKA_D   ((uint16_t volatile *)FIO2_MASKA_D)

#define pFIO2_MASKA_S   ((uint16_t volatile *)FIO2_MASKA_S)

#define pFIO2_MASKA_T   ((uint16_t volatile *)FIO2_MASKA_T)

#define pFIO2_MASKB_C   ((uint16_t volatile *)FIO2_MASKB_C)

#define pFIO2_MASKB_D   ((uint16_t volatile *)FIO2_MASKB_D)

#define pFIO2_MASKB_S   ((uint16_t volatile *)FIO2_MASKB_S)

#define pFIO2_MASKB_T   ((uint16_t volatile *)FIO2_MASKB_T)

#define pFIO2_POLAR   ((uint16_t volatile *)FIO2_POLAR)

#define pILAT   ((uint32_t volatile *)ILAT)

#define pIMASK   ((uint32_t volatile *)IMASK)

#define pIMDMA_D0_CONFIG   ((uint16_t volatile *)IMDMA_D0_CONFIG)

#define pIMDMA_D0_CURR_ADDR   ((void * volatile *)IMDMA_D0_CURR_ADDR)

#define pIMDMA_D0_CURR_DESC_PTR   ((void * volatile *)IMDMA_D0_CURR_DESC_PTR)

#define pIMDMA_D0_CURR_X_COUNT   ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT)

#define pIMDMA_D0_CURR_Y_COUNT   ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT)

#define pIMDMA_D0_IRQ_STATUS   ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS)

#define pIMDMA_D0_NEXT_DESC_PTR   ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR)

#define pIMDMA_D0_START_ADDR   ((void * volatile *)IMDMA_D0_START_ADDR)

#define pIMDMA_D0_X_COUNT   ((uint16_t volatile *)IMDMA_D0_X_COUNT)

#define pIMDMA_D0_X_MODIFY   ((uint16_t volatile *)IMDMA_D0_X_MODIFY)

#define pIMDMA_D0_Y_COUNT   ((uint16_t volatile *)IMDMA_D0_Y_COUNT)

#define pIMDMA_D0_Y_MODIFY   ((uint16_t volatile *)IMDMA_D0_Y_MODIFY)

#define pIMDMA_D1_CONFIG   ((uint16_t volatile *)IMDMA_D1_CONFIG)

#define pIMDMA_D1_CURR_ADDR   ((void * volatile *)IMDMA_D1_CURR_ADDR)

#define pIMDMA_D1_CURR_DESC_PTR   ((void * volatile *)IMDMA_D1_CURR_DESC_PTR)

#define pIMDMA_D1_CURR_X_COUNT   ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT)

#define pIMDMA_D1_CURR_Y_COUNT   ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT)

#define pIMDMA_D1_IRQ_STATUS   ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS)

#define pIMDMA_D1_NEXT_DESC_PTR   ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR)

#define pIMDMA_D1_START_ADDR   ((void * volatile *)IMDMA_D1_START_ADDR)

#define pIMDMA_D1_X_COUNT   ((uint16_t volatile *)IMDMA_D1_X_COUNT)

#define pIMDMA_D1_X_MODIFY   ((uint16_t volatile *)IMDMA_D1_X_MODIFY)

#define pIMDMA_D1_Y_COUNT   ((uint16_t volatile *)IMDMA_D1_Y_COUNT)

#define pIMDMA_D1_Y_MODIFY   ((uint16_t volatile *)IMDMA_D1_Y_MODIFY)

#define pIMDMA_S0_CONFIG   ((uint16_t volatile *)IMDMA_S0_CONFIG)

#define pIMDMA_S0_CURR_ADDR   ((void * volatile *)IMDMA_S0_CURR_ADDR)

#define pIMDMA_S0_CURR_DESC_PTR   ((void * volatile *)IMDMA_S0_CURR_DESC_PTR)

#define pIMDMA_S0_CURR_X_COUNT   ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT)

#define pIMDMA_S0_CURR_Y_COUNT   ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT)

#define pIMDMA_S0_IRQ_STATUS   ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS)

#define pIMDMA_S0_NEXT_DESC_PTR   ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR)

#define pIMDMA_S0_START_ADDR   ((void * volatile *)IMDMA_S0_START_ADDR)

#define pIMDMA_S0_X_COUNT   ((uint16_t volatile *)IMDMA_S0_X_COUNT)

#define pIMDMA_S0_X_MODIFY   ((uint16_t volatile *)IMDMA_S0_X_MODIFY)

#define pIMDMA_S0_Y_COUNT   ((uint16_t volatile *)IMDMA_S0_Y_COUNT)

#define pIMDMA_S0_Y_MODIFY   ((uint16_t volatile *)IMDMA_S0_Y_MODIFY)

#define pIMDMA_S1_CONFIG   ((uint16_t volatile *)IMDMA_S1_CONFIG)

#define pIMDMA_S1_CURR_ADDR   ((void * volatile *)IMDMA_S1_CURR_ADDR)

#define pIMDMA_S1_CURR_DESC_PTR   ((void * volatile *)IMDMA_S1_CURR_DESC_PTR)

#define pIMDMA_S1_CURR_X_COUNT   ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT)

#define pIMDMA_S1_CURR_Y_COUNT   ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT)

#define pIMDMA_S1_IRQ_STATUS   ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS)

#define pIMDMA_S1_NEXT_DESC_PTR   ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR)

#define pIMDMA_S1_START_ADDR   ((void * volatile *)IMDMA_S1_START_ADDR)

#define pIMDMA_S1_X_COUNT   ((uint16_t volatile *)IMDMA_S1_X_COUNT)

#define pIMDMA_S1_X_MODIFY   ((uint16_t volatile *)IMDMA_S1_X_MODIFY)

#define pIMDMA_S1_Y_COUNT   ((uint16_t volatile *)IMDMA_S1_Y_COUNT)

#define pIMDMA_S1_Y_MODIFY   ((uint16_t volatile *)IMDMA_S1_Y_MODIFY)

#define pIPEND   ((uint32_t volatile *)IPEND)

#define pIPRIO   ((uint32_t volatile *)IPRIO)

#define pMDMA1_D0_CONFIG   ((uint16_t volatile *)MDMA1_D0_CONFIG)

#define pMDMA1_D0_CURR_ADDR   ((void * volatile *)MDMA1_D0_CURR_ADDR)

#define pMDMA1_D0_CURR_DESC_PTR   ((void * volatile *)MDMA1_D0_CURR_DESC_PTR)

#define pMDMA1_D0_CURR_X_COUNT   ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT)

#define pMDMA1_D0_CURR_Y_COUNT   ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT)

#define pMDMA1_D0_IRQ_STATUS   ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)

#define pMDMA1_D0_NEXT_DESC_PTR   ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)

#define pMDMA1_D0_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP)

#define pMDMA1_D0_START_ADDR   ((void * volatile *)MDMA1_D0_START_ADDR)

#define pMDMA1_D0_X_COUNT   ((uint16_t volatile *)MDMA1_D0_X_COUNT)

#define pMDMA1_D0_X_MODIFY   ((uint16_t volatile *)MDMA1_D0_X_MODIFY)

#define pMDMA1_D0_Y_COUNT   ((uint16_t volatile *)MDMA1_D0_Y_COUNT)

#define pMDMA1_D0_Y_MODIFY   ((uint16_t volatile *)MDMA1_D0_Y_MODIFY)

#define pMDMA1_D1_CONFIG   ((uint16_t volatile *)MDMA1_D1_CONFIG)

#define pMDMA1_D1_CURR_ADDR   ((void * volatile *)MDMA1_D1_CURR_ADDR)

#define pMDMA1_D1_CURR_DESC_PTR   ((void * volatile *)MDMA1_D1_CURR_DESC_PTR)

#define pMDMA1_D1_CURR_X_COUNT   ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT)

#define pMDMA1_D1_CURR_Y_COUNT   ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT)

#define pMDMA1_D1_IRQ_STATUS   ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS)

#define pMDMA1_D1_NEXT_DESC_PTR   ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)

#define pMDMA1_D1_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP)

#define pMDMA1_D1_START_ADDR   ((void * volatile *)MDMA1_D1_START_ADDR)

#define pMDMA1_D1_X_COUNT   ((uint16_t volatile *)MDMA1_D1_X_COUNT)

#define pMDMA1_D1_X_MODIFY   ((uint16_t volatile *)MDMA1_D1_X_MODIFY)

#define pMDMA1_D1_Y_COUNT   ((uint16_t volatile *)MDMA1_D1_Y_COUNT)

#define pMDMA1_D1_Y_MODIFY   ((uint16_t volatile *)MDMA1_D1_Y_MODIFY)

#define pMDMA1_S0_CONFIG   ((uint16_t volatile *)MDMA1_S0_CONFIG)

#define pMDMA1_S0_CURR_ADDR   ((void * volatile *)MDMA1_S0_CURR_ADDR)

#define pMDMA1_S0_CURR_DESC_PTR   ((void * volatile *)MDMA1_S0_CURR_DESC_PTR)

#define pMDMA1_S0_CURR_X_COUNT   ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT)

#define pMDMA1_S0_CURR_Y_COUNT   ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT)

#define pMDMA1_S0_IRQ_STATUS   ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS)

#define pMDMA1_S0_NEXT_DESC_PTR   ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)

#define pMDMA1_S0_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP)

#define pMDMA1_S0_START_ADDR   ((void * volatile *)MDMA1_S0_START_ADDR)

#define pMDMA1_S0_X_COUNT   ((uint16_t volatile *)MDMA1_S0_X_COUNT)

#define pMDMA1_S0_X_MODIFY   ((uint16_t volatile *)MDMA1_S0_X_MODIFY)

#define pMDMA1_S0_Y_COUNT   ((uint16_t volatile *)MDMA1_S0_Y_COUNT)

#define pMDMA1_S0_Y_MODIFY   ((uint16_t volatile *)MDMA1_S0_Y_MODIFY)

#define pMDMA1_S1_CONFIG   ((uint16_t volatile *)MDMA1_S1_CONFIG)

#define pMDMA1_S1_CURR_ADDR   ((void * volatile *)MDMA1_S1_CURR_ADDR)

#define pMDMA1_S1_CURR_DESC_PTR   ((void * volatile *)MDMA1_S1_CURR_DESC_PTR)

#define pMDMA1_S1_CURR_X_COUNT   ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT)

#define pMDMA1_S1_CURR_Y_COUNT   ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT)

#define pMDMA1_S1_IRQ_STATUS   ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS)

#define pMDMA1_S1_NEXT_DESC_PTR   ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)

#define pMDMA1_S1_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP)

#define pMDMA1_S1_START_ADDR   ((void * volatile *)MDMA1_S1_START_ADDR)

#define pMDMA1_S1_X_COUNT   ((uint16_t volatile *)MDMA1_S1_X_COUNT)

#define pMDMA1_S1_X_MODIFY   ((uint16_t volatile *)MDMA1_S1_X_MODIFY)

#define pMDMA1_S1_Y_COUNT   ((uint16_t volatile *)MDMA1_S1_Y_COUNT)

#define pMDMA1_S1_Y_MODIFY   ((uint16_t volatile *)MDMA1_S1_Y_MODIFY)

#define pMDMA2_D0_CONFIG   ((uint16_t volatile *)MDMA2_D0_CONFIG)

#define pMDMA2_D0_CURR_ADDR   ((void * volatile *)MDMA2_D0_CURR_ADDR)

#define pMDMA2_D0_CURR_DESC_PTR   ((void * volatile *)MDMA2_D0_CURR_DESC_PTR)

#define pMDMA2_D0_CURR_X_COUNT   ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT)

#define pMDMA2_D0_CURR_Y_COUNT   ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT)

#define pMDMA2_D0_IRQ_STATUS   ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS)

#define pMDMA2_D0_NEXT_DESC_PTR   ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR)

#define pMDMA2_D0_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP)

#define pMDMA2_D0_START_ADDR   ((void * volatile *)MDMA2_D0_START_ADDR)

#define pMDMA2_D0_X_COUNT   ((uint16_t volatile *)MDMA2_D0_X_COUNT)

#define pMDMA2_D0_X_MODIFY   ((uint16_t volatile *)MDMA2_D0_X_MODIFY)

#define pMDMA2_D0_Y_COUNT   ((uint16_t volatile *)MDMA2_D0_Y_COUNT)

#define pMDMA2_D0_Y_MODIFY   ((uint16_t volatile *)MDMA2_D0_Y_MODIFY)

#define pMDMA2_D1_CONFIG   ((uint16_t volatile *)MDMA2_D1_CONFIG)

#define pMDMA2_D1_CURR_ADDR   ((void * volatile *)MDMA2_D1_CURR_ADDR)

#define pMDMA2_D1_CURR_DESC_PTR   ((void * volatile *)MDMA2_D1_CURR_DESC_PTR)

#define pMDMA2_D1_CURR_X_COUNT   ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT)

#define pMDMA2_D1_CURR_Y_COUNT   ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT)

#define pMDMA2_D1_IRQ_STATUS   ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS)

#define pMDMA2_D1_NEXT_DESC_PTR   ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR)

#define pMDMA2_D1_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP)

#define pMDMA2_D1_START_ADDR   ((void * volatile *)MDMA2_D1_START_ADDR)

#define pMDMA2_D1_X_COUNT   ((uint16_t volatile *)MDMA2_D1_X_COUNT)

#define pMDMA2_D1_X_MODIFY   ((uint16_t volatile *)MDMA2_D1_X_MODIFY)

#define pMDMA2_D1_Y_COUNT   ((uint16_t volatile *)MDMA2_D1_Y_COUNT)

#define pMDMA2_D1_Y_MODIFY   ((uint16_t volatile *)MDMA2_D1_Y_MODIFY)

#define pMDMA2_S0_CONFIG   ((uint16_t volatile *)MDMA2_S0_CONFIG)

#define pMDMA2_S0_CURR_ADDR   ((void * volatile *)MDMA2_S0_CURR_ADDR)

#define pMDMA2_S0_CURR_DESC_PTR   ((void * volatile *)MDMA2_S0_CURR_DESC_PTR)

#define pMDMA2_S0_CURR_X_COUNT   ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT)

#define pMDMA2_S0_CURR_Y_COUNT   ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT)

#define pMDMA2_S0_IRQ_STATUS   ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS)

#define pMDMA2_S0_NEXT_DESC_PTR   ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR)

#define pMDMA2_S0_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP)

#define pMDMA2_S0_START_ADDR   ((void * volatile *)MDMA2_S0_START_ADDR)

#define pMDMA2_S0_X_COUNT   ((uint16_t volatile *)MDMA2_S0_X_COUNT)

#define pMDMA2_S0_X_MODIFY   ((uint16_t volatile *)MDMA2_S0_X_MODIFY)

#define pMDMA2_S0_Y_COUNT   ((uint16_t volatile *)MDMA2_S0_Y_COUNT)

#define pMDMA2_S0_Y_MODIFY   ((uint16_t volatile *)MDMA2_S0_Y_MODIFY)

#define pMDMA2_S1_CONFIG   ((uint16_t volatile *)MDMA2_S1_CONFIG)

#define pMDMA2_S1_CURR_ADDR   ((void * volatile *)MDMA2_S1_CURR_ADDR)

#define pMDMA2_S1_CURR_DESC_PTR   ((void * volatile *)MDMA2_S1_CURR_DESC_PTR)

#define pMDMA2_S1_CURR_X_COUNT   ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT)

#define pMDMA2_S1_CURR_Y_COUNT   ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT)

#define pMDMA2_S1_IRQ_STATUS   ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS)

#define pMDMA2_S1_NEXT_DESC_PTR   ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR)

#define pMDMA2_S1_PERIPHERAL_MAP   ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP)

#define pMDMA2_S1_START_ADDR   ((void * volatile *)MDMA2_S1_START_ADDR)

#define pMDMA2_S1_X_COUNT   ((uint16_t volatile *)MDMA2_S1_X_COUNT)

#define pMDMA2_S1_X_MODIFY   ((uint16_t volatile *)MDMA2_S1_X_MODIFY)

#define pMDMA2_S1_Y_COUNT   ((uint16_t volatile *)MDMA2_S1_Y_COUNT)

#define pMDMA2_S1_Y_MODIFY   ((uint16_t volatile *)MDMA2_S1_Y_MODIFY)

#define pPLL_CTL   ((uint16_t volatile *)PLL_CTL)

#define pPLL_DIV   ((uint16_t volatile *)PLL_DIV)

#define pPLL_LOCKCNT   ((uint16_t volatile *)PLL_LOCKCNT)

#define pPLL_STAT   ((uint16_t volatile *)PLL_STAT)

#define pSPI_BAUD   ((uint16_t volatile *)SPI_BAUD)

#define pSPI_CTL   ((uint16_t volatile *)SPI_CTL)

#define pSPI_FLG   ((uint16_t volatile *)SPI_FLG)

#define pSPI_RDBR   ((uint16_t volatile *)SPI_RDBR)

#define pSPI_SHADOW   ((uint16_t volatile *)SPI_SHADOW)

#define pSPI_STAT   ((uint16_t volatile *)SPI_STAT)

#define pSPI_TDBR   ((uint16_t volatile *)SPI_TDBR)

#define pSPORT0_CHNL   ((uint16_t volatile *)SPORT0_CHNL)

#define pSPORT0_MCMC1   ((uint16_t volatile *)SPORT0_MCMC1)

#define pSPORT0_MCMC2   ((uint16_t volatile *)SPORT0_MCMC2)

#define pSPORT0_MRCS0   ((uint32_t volatile *)SPORT0_MRCS0)

#define pSPORT0_MRCS1   ((uint32_t volatile *)SPORT0_MRCS1)

#define pSPORT0_MRCS2   ((uint32_t volatile *)SPORT0_MRCS2)

#define pSPORT0_MRCS3   ((uint32_t volatile *)SPORT0_MRCS3)

#define pSPORT0_MTCS0   ((uint32_t volatile *)SPORT0_MTCS0)

#define pSPORT0_MTCS1   ((uint32_t volatile *)SPORT0_MTCS1)

#define pSPORT0_MTCS2   ((uint32_t volatile *)SPORT0_MTCS2)

#define pSPORT0_MTCS3   ((uint32_t volatile *)SPORT0_MTCS3)

#define pSPORT0_RCLKDIV   ((uint16_t volatile *)SPORT0_RCLKDIV)

#define pSPORT0_RCR1   ((uint16_t volatile *)SPORT0_RCR1)

#define pSPORT0_RCR2   ((uint16_t volatile *)SPORT0_RCR2)

#define pSPORT0_RFSDIV   ((uint16_t volatile *)SPORT0_RFSDIV)

#define pSPORT0_RX   ((uint32_t volatile *)SPORT0_RX)

#define pSPORT0_STAT   ((uint16_t volatile *)SPORT0_STAT)

#define pSPORT0_TCLKDIV   ((uint16_t volatile *)SPORT0_TCLKDIV)

#define pSPORT0_TCR1   ((uint16_t volatile *)SPORT0_TCR1)

#define pSPORT0_TCR2   ((uint16_t volatile *)SPORT0_TCR2)

#define pSPORT0_TFSDIV   ((uint16_t volatile *)SPORT0_TFSDIV)

#define pSPORT0_TX   ((uint32_t volatile *)SPORT0_TX)

#define pSPORT1_CHNL   ((uint16_t volatile *)SPORT1_CHNL)

#define pSPORT1_MCMC1   ((uint16_t volatile *)SPORT1_MCMC1)

#define pSPORT1_MCMC2   ((uint16_t volatile *)SPORT1_MCMC2)

#define pSPORT1_MRCS0   ((uint32_t volatile *)SPORT1_MRCS0)

#define pSPORT1_MRCS1   ((uint32_t volatile *)SPORT1_MRCS1)

#define pSPORT1_MRCS2   ((uint32_t volatile *)SPORT1_MRCS2)

#define pSPORT1_MRCS3   ((uint32_t volatile *)SPORT1_MRCS3)

#define pSPORT1_MTCS0   ((uint32_t volatile *)SPORT1_MTCS0)

#define pSPORT1_MTCS1   ((uint32_t volatile *)SPORT1_MTCS1)

#define pSPORT1_MTCS2   ((uint32_t volatile *)SPORT1_MTCS2)

#define pSPORT1_MTCS3   ((uint32_t volatile *)SPORT1_MTCS3)

#define pSPORT1_RCLKDIV   ((uint16_t volatile *)SPORT1_RCLKDIV)

#define pSPORT1_RCR1   ((uint16_t volatile *)SPORT1_RCR1)

#define pSPORT1_RCR2   ((uint16_t volatile *)SPORT1_RCR2)

#define pSPORT1_RFSDIV   ((uint16_t volatile *)SPORT1_RFSDIV)

#define pSPORT1_RX   ((uint32_t volatile *)SPORT1_RX)

#define pSPORT1_STAT   ((uint16_t volatile *)SPORT1_STAT)

#define pSPORT1_TCLKDIV   ((uint16_t volatile *)SPORT1_TCLKDIV)

#define pSPORT1_TCR1   ((uint16_t volatile *)SPORT1_TCR1)

#define pSPORT1_TCR2   ((uint16_t volatile *)SPORT1_TCR2)

#define pSPORT1_TFSDIV   ((uint16_t volatile *)SPORT1_TFSDIV)

#define pSPORT1_TX   ((uint32_t volatile *)SPORT1_TX)

#define pTCNTL   ((uint32_t volatile *)TCNTL)

#define pTCOUNT   ((uint32_t volatile *)TCOUNT)

#define pTIMER0_CONFIG   ((uint16_t volatile *)TIMER0_CONFIG)

#define pTIMER0_COUNTER   ((uint32_t volatile *)TIMER0_COUNTER)

#define pTIMER0_PERIOD   ((uint32_t volatile *)TIMER0_PERIOD)

#define pTIMER0_WIDTH   ((uint32_t volatile *)TIMER0_WIDTH)

#define pTIMER10_CONFIG   ((uint16_t volatile *)TIMER10_CONFIG)

#define pTIMER10_COUNTER   ((uint32_t volatile *)TIMER10_COUNTER)

#define pTIMER10_PERIOD   ((uint32_t volatile *)TIMER10_PERIOD)

#define pTIMER10_WIDTH   ((uint32_t volatile *)TIMER10_WIDTH)

#define pTIMER11_CONFIG   ((uint16_t volatile *)TIMER11_CONFIG)

#define pTIMER11_COUNTER   ((uint32_t volatile *)TIMER11_COUNTER)

#define pTIMER11_PERIOD   ((uint32_t volatile *)TIMER11_PERIOD)

#define pTIMER11_WIDTH   ((uint32_t volatile *)TIMER11_WIDTH)

#define pTIMER1_CONFIG   ((uint16_t volatile *)TIMER1_CONFIG)

#define pTIMER1_COUNTER   ((uint32_t volatile *)TIMER1_COUNTER)

#define pTIMER1_PERIOD   ((uint32_t volatile *)TIMER1_PERIOD)

#define pTIMER1_WIDTH   ((uint32_t volatile *)TIMER1_WIDTH)

#define pTIMER2_CONFIG   ((uint16_t volatile *)TIMER2_CONFIG)

#define pTIMER2_COUNTER   ((uint32_t volatile *)TIMER2_COUNTER)

#define pTIMER2_PERIOD   ((uint32_t volatile *)TIMER2_PERIOD)

#define pTIMER2_WIDTH   ((uint32_t volatile *)TIMER2_WIDTH)

#define pTIMER3_CONFIG   ((uint16_t volatile *)TIMER3_CONFIG)

#define pTIMER3_COUNTER   ((uint32_t volatile *)TIMER3_COUNTER)

#define pTIMER3_PERIOD   ((uint32_t volatile *)TIMER3_PERIOD)

#define pTIMER3_WIDTH   ((uint32_t volatile *)TIMER3_WIDTH)

#define pTIMER4_CONFIG   ((uint16_t volatile *)TIMER4_CONFIG)

#define pTIMER4_COUNTER   ((uint32_t volatile *)TIMER4_COUNTER)

#define pTIMER4_PERIOD   ((uint32_t volatile *)TIMER4_PERIOD)

#define pTIMER4_WIDTH   ((uint32_t volatile *)TIMER4_WIDTH)

#define pTIMER5_CONFIG   ((uint16_t volatile *)TIMER5_CONFIG)

#define pTIMER5_COUNTER   ((uint32_t volatile *)TIMER5_COUNTER)

#define pTIMER5_PERIOD   ((uint32_t volatile *)TIMER5_PERIOD)

#define pTIMER5_WIDTH   ((uint32_t volatile *)TIMER5_WIDTH)

#define pTIMER6_CONFIG   ((uint16_t volatile *)TIMER6_CONFIG)

#define pTIMER6_COUNTER   ((uint32_t volatile *)TIMER6_COUNTER)

#define pTIMER6_PERIOD   ((uint32_t volatile *)TIMER6_PERIOD)

#define pTIMER6_WIDTH   ((uint32_t volatile *)TIMER6_WIDTH)

#define pTIMER7_CONFIG   ((uint16_t volatile *)TIMER7_CONFIG)

#define pTIMER7_COUNTER   ((uint32_t volatile *)TIMER7_COUNTER)

#define pTIMER7_PERIOD   ((uint32_t volatile *)TIMER7_PERIOD)

#define pTIMER7_WIDTH   ((uint32_t volatile *)TIMER7_WIDTH)

#define pTIMER8_CONFIG   ((uint16_t volatile *)TIMER8_CONFIG)

#define pTIMER8_COUNTER   ((uint32_t volatile *)TIMER8_COUNTER)

#define pTIMER8_PERIOD   ((uint32_t volatile *)TIMER8_PERIOD)

#define pTIMER8_WIDTH   ((uint32_t volatile *)TIMER8_WIDTH)

#define pTIMER9_CONFIG   ((uint16_t volatile *)TIMER9_CONFIG)

#define pTIMER9_COUNTER   ((uint32_t volatile *)TIMER9_COUNTER)

#define pTIMER9_PERIOD   ((uint32_t volatile *)TIMER9_PERIOD)

#define pTIMER9_WIDTH   ((uint32_t volatile *)TIMER9_WIDTH)

#define pTMRS4_DISABLE   ((uint32_t volatile *)TMRS4_DISABLE)

#define pTMRS4_ENABLE   ((uint32_t volatile *)TMRS4_ENABLE)

#define pTMRS4_STATUS   ((uint32_t volatile *)TMRS4_STATUS)

#define pTMRS8_DISABLE   ((uint32_t volatile *)TMRS8_DISABLE)

#define pTMRS8_ENABLE   ((uint32_t volatile *)TMRS8_ENABLE)

#define pTMRS8_STATUS   ((uint32_t volatile *)TMRS8_STATUS)

#define pTPERIOD   ((uint32_t volatile *)TPERIOD)

#define pTSCALE   ((uint32_t volatile *)TSCALE)

#define pVR_CTL   ((uint16_t volatile *)VR_CTL)

#define pWDOGA_CNT   ((uint32_t volatile *)WDOGA_CNT)

#define pWDOGA_CTL   ((uint16_t volatile *)WDOGA_CTL)

#define pWDOGA_STAT   ((uint32_t volatile *)WDOGA_STAT)

#define pWDOGB_CNT   ((uint32_t volatile *)WDOGB_CNT)

#define pWDOGB_CTL   ((uint16_t volatile *)WDOGB_CTL)

#define pWDOGB_STAT   ((uint32_t volatile *)WDOGB_STAT)


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